About harerod

harerod · 2021-08-16

I have designed a board with four seemingly identical motor drivers. The four L6472 are connected to an STM32-MCU via one SPI-interface, chipselect is handled by GPIO. They share a common reset signal, also GPIO. Because of the pull-downs on /STBY_RE...

harerod · 2013-05-29

Posted on May 29, 2013 at 15:22Hello, we want to implement a pulse generator with Timer1, clocked by SYCLK. For marketing reasons we'd prefer a granularity of 10ns, therefor we'd set SYSCLOCK to 100MHz. At the same time we'll need a USB CDC for our...

harerod · 2021-09-01

Christiana,thank you for your confirmation. The "offending" circuits have SW activated when reset goes inactive. I will take this information into account when redesigning the next board revision. Which will take a while, because of most semiconducto...

harerod · 2021-08-17

Hello Peter,following up on your findings, we can assume that the input level at power-up on the SW-input is different for U702/U703 than for U602/U603. Although I haven't found it spelled out in the datasheet, I could come to assume the following ha...

harerod · 2021-08-16

Hello Peter,thanks for having a close look at this. U703-SW is externally connected to a normally closed limit switch to GND. U702-SW is connected to an Encoder Index Track, which also works as a switch to GND. To be honest - this wiring is less than...

harerod · 2013-05-30

Posted on May 30, 2013 at 11:01Thanks Richard, for hunting this piece of information down and closing that approach to separating SYSCLOCK from USBCLOCK. Quoting AN2606 (Which I didn't consult, because my brain was down a different track) was a very...

harerod · 2013-05-29

Posted on May 29, 2013 at 16:07Thanks for feedback. It would be interesting to know, if the bootloader actually calculates the HSE clock. At least it works with HSE 8..25MHz, don't know if ''from''. Maybe I'll remove the crystal sometime... If nobod...

User statistics

User Activity

What causes L6472 to power up / leave reset with bridges active?

ST32F407 ''HSI as USB CDC'' or ''Separating SYCLK from USBCLK''

Re: What causes L6472 to power up / leave reset with bridges active?

Re: What causes L6472 to power up / leave reset with bridges active?

Re: What causes L6472 to power up / leave reset with bridges active?

Re: ST32F407 ''HSI as USB CDC'' or ''Separating SYCLK from USBCLK''

Re: ST32F407 ''HSI as USB CDC'' or ''Separating SYCLK from USBCLK''