ADC in dual mode with sampling frequency of 10.66 MS/s (5.33 per ADC).The System clock is set to 120 MHzThe ADC clock is set to 80MHzThe ADC1 IN8 ext3 is trigged by TIM2 CC2.The ADC data transfet is done though DMA2 CH3
I use Atollic TrueSTUDIO v9.0.1 for a STM32L496RG project.I use the LL_RCC_DeInit() function and have an issue when activation of Optimisation option -Ofast or -O3 .To fix the issue I had to add the key word volatile (see code below).ErrorStatus LL...
Posted on September 14, 2015 at 18:12I have an EXTI programmed on PortB line8 that works as expected when a rising edge is found on GPIO_IN8.Unfortunaltely sometimes, when I reset the GPIO_Pin15 of port B by doing GPIOB->BRR = GPIO_Pin_15 then t...
Posted on July 22, 2015 at 18:20
I need to disable the VVDA monitor at power down reset (PDR).
To do this, it needs to write in the option bytes register.
I did the following code.
//Disable VDDA MONITOR in option bit
uin...
Posted on September 15, 2015 at 14:40> Even if there's no ''hard'' short, you still may have capacitive coupling between the pins, or they can be coupled through some common ground resistance (which rises the questions of proper power/ground distrib...
Posted on July 23, 2015 at 12:58
Thanks for your advices.
Now it's work.
Below the working code.
//Disable VDDA MONITOR in option bit, to avoid Power Down Reset when VDDA is going down, only VDD is needed
uint8_t UserByte = FLAS...
Posted on March 13, 2015 at 13:07I did a test and conclusion is that going back to Read Protection Level 0 erases all pages even those set as write protected.I also noticed that if you have previously activated the write protection on some pages t...
Posted on November 28, 2014 at 09:53The issue was due to the Segger Jlink probe that didn't support the flash size over 256k. From the new Jlink software 4.94g it is OK now for the STM32F303RE.Thanks to SEGGER support.
Posted on October 21, 2013 at 17:45It happens in the startup_stm32f30x.s file at function LoopCopyDataInit.After a while it crashes.CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4LoopCopyDataInit: ldr r0, =_sdata ld...
