Hello All,testing conditions for initial question are not representative to obtain latency of ISR.Running at 32MHz Sysclock add extra flash wait state and different AHB and APBx clocks add synchronization delay between buses which caused variation in...
Hello,
your question is mixing LSE and HSE crystal. However, I need to say that 10pF mentioned in DS is too much and would be better not include any number in DS regarding this matter (as it depends on package, layout,.. tolerance PCB).From our exper...
