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swu.1
Associate II
since ‎2022-09-27
‎2023-06-14

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  • 6 Posts
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User Activity

Why RAM and System RAM shall be reset when system boot up?

2022-12-28
Hi expert,I am using Stellar SR6 P7 line, e.g. SR6P7C8. According to the SDK there is RAM and System RAM reset operation when system boot,/* Initialize memories protected by ECC */ bl _raminit bl _sysraminitI want to get more information abou...

Where can I get the EIRQ configuration for Stellar reference board?

2022-11-21
Hi,Where can I get the EIRQ configuration for Stellar reference board? I'd like to config the GPIO button to receive interrupt. Thanks.

Does Cluster Local RAM support exclusive access with shareable attribute (as well as non-cacheable)

2022-11-15
Hi expert,I am using Stellar SR6 P7 line, e.g. SR6P7C8.I found atomic operation will always fail on Cluster Local Ram (0x60000000 or 0x60400000) when shareable is set as well as non-cachable. But such opeation can pass on System Ram (0x64000000).Any ...

Is Symmetric Multi-Processing (SMP) supported on Stellar SR6 P7 R52+ cores

2022-09-28
There are several R52+ cores available in Stellar SR6 P7 line, e.g. SR6P7C8.I have question about the Symmetric Multi-Processing (SMP) support on these R52+ cores. Is SMP available inside R52+ cluster or among R52+ clusters?
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