Posted on August 03, 2017 at 10:36 I'm trying to reprogram the NVM (flash bank 2) while running code from flash bank 1 in STM32L071CB microcontroller. As AN4808 and AN4767 stand, 'the memory interface is capable of reading both banks in parallel,...
Posted on September 21, 2017 at 12:05Hi,thank you for your answer. I had to suspend my project for a while due to some (not uC realated) reasons, but when the project resumes, I'll rewrite the code. I'll probably just stick to the single programming...
Posted on August 04, 2017 at 10:11Well I'm really confused right now. Today I've started debugging the same code as yesterday and FWWERR disappeared. I've tried both versions - with debugger attached and standalone. I'm trying to recreate the situat...
Posted on August 03, 2017 at 15:00Thans for your reply.I've got CPUID = 0x410CC601 and DEVID = 0x447. It stands for ARM rev0 / arch. ARMv6-M / Cortex M0+ core / STM32L0 family / patch 1 / Device cat. 5.Reading DBGMCU->IDCODE & 0xFFFF0000 (REV_ID) gi...
