I am confused with the SPI operation particularly the raising CS after each byte (which isn't shown in the data sheet figures). I can get the motor to work, but as an example this is what I have to do to send a simple move command. The data is (in he...
This is driving me crazy. First time with this processor. I have AFR2 and NAFR2 set properly for AIN2 operation. I can verify that in the watch window and the disassembly window looks like it is working as expected. If I change the channel to AIN7 I ...
Posted on July 28, 2017 at 19:23Is there a recommended pad layout for the POWERSO36 package? Ap note AN668 regarding this package has a detailed layout for the POWERSO20 package with measurement data, but not the POWERSO36.
Yes, I got it to work. I was using the L6470 eval board and an SPI host adapter to test out the operation. I changed from sending the bytes one at a time to sending in the adapter batch mode and it worked. Not sure what the difference was. Knowing th...
Yes. The clock goes to its high idle state between bytes. What I need to verify is the proper sequence. It looks like sending each byte separately with CS going high in between should work. Correct? If that is the case then there is probably somethin...
Figured it out. It had to do with the proper sequence to unlock and enable the option byte modification. There are several documents that supposedly explain how to do this, but only one tells the complete story (4.5.3 reference): unlock the data memo...
