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GHale.1 · 2022-12-23

GHale.1 · 2022-12-23

So you are confirming you must use the 5 wire JTAG interface mode not serial wire (SWD) to use boundary scan?SWD only uses SWCLK(TCK) and TMS(SWDIO) and after the SWD sequence the chip disables boundary scan TAP. According to the documentation, stm32...

GHale.1 · 2022-12-23

Yes unless I misread it,the reference manual says to use boundary scan NJTRST must be held low. ST doesn't seem to like boundary scan

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After reading the stm32F401 reference document, it appears jtag boundary scan is not supported unless using full 5 wire JTAG interface and SWD will prevent access to this feature. Can I get confirmation on this?

Re: After reading the stm32F401 reference document, it appears jtag boundary scan is not supported unless using full 5 wire JTAG interface and SWD will prevent access to this feature. Can I get confirmation on this?

Re: After reading the stm32F401 reference document, it appears jtag boundary scan is not supported unless using full 5 wire JTAG interface and SWD will prevent access to this feature. Can I get confirmation on this?