About HPiG

HPiG · 2022-03-31

Setup is as follows:ADC1 & 2 in 'Dual regular simultaneous mode only'DMA1 stream 0 used to transfer ADC data to AXI SRAM buffer (40000 32 bit values), DMA circular mode.Using 'HAL_ADC_ConvHalfCpltCallback' to signal half buffer filled and 'HAL_ADC_Co...

HPiG · 2022-10-14

Problem solved (been ignored for a while). The ADC:s must be calibrated before startup, which they weren't.After runningHAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED)last in MX_ADC1_Init for ADC1 the problem seems t...

HPiG · 2022-04-13

ADC data gaps:The above image shows data from ADC1 (blue) and ADC2 (orange). A/D values on Y axis.The horizontal white stripes thus representing gaps in ADC data.The ADC1 graph shows gaps at 4k intervals (it continues at 8191, 12287 and so on) but th...

HPiG · 2022-04-12

The VDDA/VREF+ pins actually had capacitors, they were in another corner of the circuit diagram:I have tested with and without the EMI filter and I have shorted VREF+ and VDDA to each other on the MCU pins, no change. The PCB layout looksquite airigh...

HPiG · 2022-04-01

I looked at both links, and they seem to describe both the problem and the solution.This is a custom board.Hope the image is readable, looks shrinked.VREF+ and VDDA are tied together and derived from +3V3 via an EMI filter, without any capacitor.I wi...

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Value gaps in DMA transferred ADC data

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