Posted on April 23, 2013 at 14:17I found more or less graceful workaround and want to share it.I reconnected memory WR pin from FSMC_NWE to FSMC_NL(NADV) and configured memory type as NOR flash and mode 2 (see p.31.5.4/''Mode 2/B - NOR Flash'' of re...

Posted on April 22, 2013 at 13:11We have the same problem ! And I ask ST enigneers, why did you designed timings such as that phase have fixed 1 HCLK ??? We missed this insidious and despicable detail and now we are puzzled over possible workaround ...