Posted on May 17, 2011 at 12:57Anyone using DMA, In section 9.3.7 of RM0008, it is written; ''The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering DMA1, this...
Posted on May 17, 2011 at 12:57Quote:Is it right that the BTF flag is set if the intrrupt get delayed? If the uC does not read the Data Register when a byte has been received, the clock continues to be active. When the second byte is received (and a...
Posted on May 17, 2011 at 12:57Quote:1) Is it correct that yours is a ''multi-master'' application - and the problem you've described occurs as you switch from master transmit to ''slave receive'' mode? 2) Have you tried - and if so - do you operat...
Posted on May 17, 2011 at 12:57Hi all, I'm using STM32F103xxx. I am having endless problems with the I2C devices, due to the presence of the Rx buffer. Sometimes, if my interrupt is delayed, Rx data is present in both the buffer and shift register. ...
Posted on May 17, 2011 at 12:53Gavin, What you need are this http://www.st.com/stonline/products/literature/rm/13902.pdf and these http://www.st.com/stonline/products/literature/um/13475.pdf http://www.st.com/stonline/products/support/micro/files/um...
