Concurrent DMA channels enabled?

[brianforde9]

Posted on January 06, 2009 at 01:29

Concurrent DMA channels enabled?

[brianforde9]

Posted on May 17, 2011 at 12:57

Anyone using DMA,

In section 9.3.7 of RM0008, it is written; ''The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering DMA1, this means that only one request must be enabled at a time. Refer to Figure 18: DMA1 request mapping.''I have not tried to use multiple DMA channels simultaneously, but from the above I am led to believe that this is not possible (i.e. the application cannot have more than one channel enabled at any given instance). Is this true, or have I mis-interpreted the above quotation? If this is not true, then what does this quatation actually mean? The alternate interpretation is that the peripherals on each channel are logically ORed, and that only one of them (for each channel) should have its DMA request active. This interpretation makes more sense, but I don't think that's what the above quotation implies. Best regards, Brian F.

[gdp123a]

Posted on May 17, 2011 at 12:57

I think it is poorly worded.

In AN2548 application note ''Using the STM32F101xx and STM32F103xx DMA controller'' it states more clearly: ''Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals connected to the same DMA channel (CH1 to CH7 in Table 1) cannot be used simultaneously with active DMA (DMA function active in the peripheral register).'' The application note gives a few examples of using the DMA with multiple channels (including a DMA from GPIO example).