Posted on May 17, 2011 at 13:15Lars, I think the problem is in your calculation of the sample time. Sorry to not debug your math, but I will show you how I calculate it. ADCCLK = 3,000,000 Hz Sampling Setting = 71.5 Cycles (assumed for all three cha...
Posted on May 17, 2011 at 13:06All, I have been in contact with ST about this and they are sticking by their recommended circuit in the figure in the datasheet. Quote:- For the reset circuit: We did not see any failure on the reset pin on the US and...
Posted on May 17, 2011 at 12:40Hello, I know that the design manual says that Vbat 'must' be connected, but is there really any reason? If the switch shown in the figures in the datasheet is true to implementation, how different is it to leave it un...
