Posted on March 21, 2017 at 19:08Hi,As you said the Cortex-M7 architecture is different from Cortex-M4. It has a 6-stage dual-issue pipeline allowing it to process 2 instruction in parallel. Unfortunately only one floating point pipe supporting sing...
Posted on March 21, 2017 at 16:32Hi Clive,Yes, I would definitely check caching, memory map and use a 32-bit timer for benchmarking.Just a minor comment: F767 has both FPU-D and FPU-S.If the compiler is configured for only single precision, it will ...
Posted on March 21, 2017 at 14:21Hello,The exact conditions and FW loop can help. Your observation is not inline with the product performances.What about the Cache/ART configuration? if you are using ITCM interface for code execution, you will need...
