Posted on May 17, 2011 at 14:24Problem solved! :) Kind of.. I found this forum thread: http://forum.raisonance.com/viewtopic.php?id=3466 and it turns out that this is a current limitation of the simulator. Weird that this was not easier to find out...
Posted on May 17, 2011 at 14:24Too bad, I was hoping that I did something wrong. I'll try in hardware as soon as I get a chance, though that might take a while. For now, I can assure that the simulator is genuinely certain that the APSR was not upda...
Posted on May 17, 2011 at 14:18My version of that document does not have that section (it's from 2007). So the conclusion is that: #1: Non-aligned memory addresses are rounded down #2: There is no rotation #3: Offsets are applied after any roundin...
Posted on May 17, 2011 at 14:18The LDR R1,[R0] was unexpected, as I thought it should rotate, but if you are right, I guess it is behaving normally. There is nothing unexpected in my original code, as long as one applies the address offset after ro...
Posted on May 17, 2011 at 14:18Hm my version of the document did not even have an A6 7.42 section :S Could you quote the text? The following code .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .section .data .align 4 .byte 0x77 var1: .word 0...
