Posted on May 17, 2011 at 13:49Hi Domen, thanks for your reply, basically the example that I use is very similar : /* IWDG timeout equal to 280 ms (the timeout may varies due to LSI frequency dispersion) */ /* Enable write access to IWDG_...
Posted on May 17, 2011 at 13:49Hi, the register CR of DBGMCU is at 0, so the bit DBG_IWDG_STOP is at 0 (0: The watchdog counter clock continues even if the core is halted, based on the datasheet). I had also tried to remove the debugger but without...
