Posted on January 14, 2012 at 22:28Hi Clive,For divide instructions, the operation would be terminated and restart after the interrupt handling is completed.If you have a memory accesses that takes long time, the processor will have to wait because ...
Posted on January 14, 2012 at 00:10Hi there, As Giovanni mentioned, the status of multiple load/store is saved in the stacked EPSR (part of the xPSR). So when the interrupt returns, it can resume from the interrupted transfer. For Cortex-M0, if a in...
Posted on August 19, 2011 at 00:55Maybe you can try to use the MPU to program the memory space as non bufferable? This should be able to disable the write buffer. Note: it will slow things down. The auxiliary control register was added in Cortex-M3 ...
Posted on June 28, 2011 at 14:30Hi there, Even without printf, you can debug a hard fault by setting a breakpoint in you hardfault handler, and when it reach the breakpoint and halted, you can examine the fault status registers. http://infocenter.ar...
Posted on May 17, 2011 at 14:20Hi PICguy, You are right that without the MPU, it is possible that a task can crash the own application. But there is a fairly good chance that the task will fail over very quickly when the stack pointer is corrupted...
