Posted on October 12, 2008 at 11:17I have tried to change the PCLK clock but without result. In the testprogram I have tried to remove the MRCC_CKSYSConfig line, and the CKTIM frequency is still the same. Can the PLL be broken on the board?
Posted on October 01, 2008 at 11:18 Hi. I’m working on the STR750 eval board for a new project, and have some trouble with the PLL. It doesn’t seem like the clock changes from 4 MHz when I multiply the clock. The interrupt should toggle a L...
Posted on September 29, 2008 at 06:08UART communications problem. Hi. I have a little strange problem with my STR750 evaluation board. I have connected the UART0 with a null modem to my computer. Made a simple code for sending data through UART but ...
