Posted on May 03, 2006 at 11:19I found the problem. I have a Xilinx part that was driving the bus at reset. It drove the P0L.1 to low. The ST10F269 documentation is very thin on information about this mode.

Posted on May 02, 2006 at 17:25Hello, I am trying to bring up a new board (ST10F269). With a scope I can see the reset in asserting low and P0L.4 asserted low. I can see the serial character (NULL) coming in on the RX line. The problem is that the T...