Posted on October 14, 2005 at 19:06I'd also like to mention that the DSP DMA transfer just prior to the IRQ0 (Timer0) and IRQ9 (DSP DMA) interrupts consumes the PCI bus for a finite amount of time since our DSP processor communicates to the STPC ove...
Posted on October 14, 2005 at 14:09I wrote about this problem in a previous post and it is still plaguing us. To date we have spent well over 2 months analyzing this problem, but due to the highly integrated nature of the STPC we have not been able ...
Posted on September 15, 2005 at 12:57Thanks for the quick reply. That fact that there is another Timer0 (IRQ0) interrupt pending is expected since this signal is basic on a periodic pulse that always runs. Our problem is that it appears the Timer0 (...
Posted on September 14, 2005 at 18:46We are running the Ardence\PharLap ETS 10.1 Operating System on a custom STPC Elite CPU board with a custom General Software BIOS. It's been working great for a couple of years. New software features to our appli...
