Posted on February 15, 2005 at 01:53The reference manual states that RCCU_CFR:Div2 is used to ensure a 50% duty cycle. What, exactly, is the duty cycle requirement for PLL1_in (CSU_CKSEL=1, CK2_16=1)? And for CLK3=CLK2 (CSU_CKSEL=0, CK2_16=1)?
Posted on February 15, 2005 at 01:44I know the Philips LPC2106 has very slow GPIO. Is the STR711 faster? My application may need to use bit-bang i/o. If MCLK, PCLK1, PCLK2 all are 48MHz, what will be the execution speed of a string of STR instructio...
