Posted on May 17, 2011 at 09:52It reset during the TX (the last packet before the reset is incomplete).

Posted on May 17, 2011 at 09:52Yes, it's sure that I have watch some exemple. The UART used to work properly. What can make the CPU resets?

Posted on May 17, 2011 at 09:52When tranmiting packet RX (From PC) and TX (To PC), after a moment (random), the CPU resets. I don't use the Watchdog. This happens either on the STR912FAW44X6 and 47X6. This is not a desired feature. What can happen t...

Posted on May 17, 2011 at 09:48Hi, My application use UART0 and a Timer (time base of 1ms) with the STR9. When I disable timer interrupt, everything is fine with the UART. When I enable the Timer, some packet are OK and randomly, it stops working. S...