Posted on May 17, 2011 at 12:02thats it, i already found it. i do not do so using other active low cs, there is no such problem ??!! i do not use the _wr or _rd signals to gate the 2 other active low cs i use. -strange- why? thanks !!!!!!!!!!!!!!!!!...
Posted on May 17, 2011 at 12:02hallo, my active high chip select on porta is much longer than the data is valid that i write to an lcd. ???!!!! in psdexpress i select active high chip select for PA7 // PSD settings // aaaaaaaaaaa Bporta_dir=0x8D; //...
Posted on May 17, 2011 at 12:01port a4 is cpld input in psd express: logic or address but changes to output sometimes ?! what if i define it as input in psd express and overwrite this settings with my soft changing the port a direction via csiop+02 ...
Posted on May 17, 2011 at 12:01there is a strange behavior: a porta pin configurated as logic input changes to output and toggles each 50 to 500ns. i do not write to the csiop-register via my progcode. is there any errata sheet for the 3233B ? thank...
