Hello everyone, what does JRT instruction, and which difference among JRT and JP instructions? Thank you!

[Philipp Krause]

jrt (which is more commonly called jra) is a relative jump instruction. It can only jump to nearby targets, takes 2 bytes and 2 cycles. jp is an absolute jump, that can jump to anywhere within a 16-bit address space. It takes 3 bytes and 1 cycle.

So in cases where you could use either it is a trade-off between code size and speed.

For more details see the "STM8 CPU programming manual":

https://www.st.com/resource/en/programming_manual/cd00161709.pdf

Philipp

[flankerus]

Yes, it's understandable. I read the manual, but unfortunately it is very short.

I thought a lot about what a would mean to False or True in the "Condition" column for instructions JRT and JRF.

Ok, JRT it's alias for JRA. 

What is JRF? Alias for NOP? 

[Philipp Krause · Accepted solution]

Well, there is table 42 with the descriptions. The one for jrf states "never jump". The instruction set entry for nop (which is separate from jrf states "see also: jrf").

It might be there for orthogonality. The reasoning for including such an instruction in the HC08 / S08 architecture was that the jrf can be used as a placeholder for a jra to some debug instrumentation code (so the debug build would have the same code locations as the non-debug build).

An interesting aspect of jrf is that it is essentially a two-byte nop for any second byte. If you put a valid 1-byte instruction into the 2nd byte, you could see jrf as a jump over that 1-byte instruction (saving 1 byte over using a jra). That can be useful in a if/else, where the else consists of just a 1-byte instruction. SDCC actually uses jrf for such an optimization.

Philipp

[flankerus]

>An interesting aspect of jrf is that it is essentially a two-byte nop for any second byte.

Curious. The Reference Manual for HCS08 for the BRN has a more detailed description:

"This instruction can be useful in instruction-based timing delays. Instruction-based timing delays are

usually discouraged because such code is not portable to systems with different clock speeds."

Does this have a relationship with STM8? I don't understand how to make a delay on the basis of JRF or BRN instruction.

   ;code of delay 1sec without JRF:
stm8/
    segment 'rom'
   ; delay 1 sec, when fCPU=2MHz
.delay:
    ld a, #$06
    ldw y, #$1a80             ; 0x61a80 = 400000 i.e. (2*10^6 MHz)/5cycles
loop:
    subw y, #$01             ; 2 cycles
    sbc a,#0                      ; 1 cycles
    jrne loop		         ; 2 cycles, flush
    ret
    end

code of delay 1sec with JRF:

stm8\
	segment 'rom'
	; delay 1 sec, when fCPU=2MHz
.delay:
	ld a, #$03
	ldw y, #$d090               ; 0x3d090=250000(dec)  i.e. (2*10^6 MHz)/8cycles
loop:  
	subw y, #$01                ; =2 cycles
	sbc a,#0                         ; =1 cycles
	jreq {exit+1}                  ; =1 cycles
exit:  
	dc.b $21, $81               ; JRF RET, =2 cycles, flush
	jra loop                          ; =2 cycles, flush
	end

It's has meaning?