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Clarification on Interrupt Map Error in STM8L052C6 Datasheet

Logan Wendholt
Associate
Posted on May 05, 2018 at 01:12

I'm currently working on an STM8L052C6 project, and am looking to set up some interrupts on Port C pins. Looking at the pin description in the datasheet

http://www.st.com/resource/en/datasheet/stm8l052c6.pdf

, it appears that Port C pins should be capable of being configured as external interrupts. However, looking at the interrupt table from the same document does not show any entry for Port C. However, it does contain entries associated with Port G and H, both of which do not exist on this particular package. So it appears there is an error in the datasheet.

With this in mind, is configuring Port C pins as external interrupts possible on the STM8L052C6 chip? If so, what is the proper IRQ number to use?

#interrupts #stm8l052c6
1 ACCEPTED SOLUTION

Accepted Solutions
Logan Wendholt
Associate
Posted on May 05, 2018 at 01:24

It appears that my answer may be in section 12.6 of the STM8L052C6 reference manual:

12.6 External interrupts

Eleven interrupt vectors are dedicated to external Interrupt events:

•

EXTIB/G - 8 lines on Port B or G: PB[7:0] or PG[7:0]EXTID/H - 8 lines on Port D or H:

PD[7:0] or PH[7:0]

•

EXTIE/F - 8 lines on Port E or F: PE[7:0] or PF[7:0]

•

EXTI0 - 6 lines on Port A/B/C/D/E/F, bit 0: Px[0]

•

EXTI1 - 5 lines on Port A/B/C/D/E, bit 1: Px[1]

•

EXTI2 - 5 lines on Port A/B/C/D/E, bit 2: Px[2]

•

EXTI3 - 5 lines on Port A/B/C/D/E, bit 3: Px[3]

•

EXTI4 - 5 lines on Port A/B/C/D/E, bit 4: Px[4]

•

EXTI5 - 5 lines on Port A/B/C/D/E, bit 5: Px[5]

•

EXTI6 - 5 lines on Port A/B/C/D/E, bit 6: Px[6]

•

EXTI7 - 5 lines on Port A/B/C/D/E, bit 7: Px[7]

So it appears that I would use EXTI0 for PC0, EXTI1 for PC1, etc. and the ambiguity of using EXTIB/G and EXTID/H instead of EXTIB and EXTID is intentional so that the same documentation can apply to all chips in the STM8L052 family.

In this case, it appears that there is no error in the datasheet, just some ambiguity that requires careful inspection to clarify. Apologies for the false alarm.

View solution in original post

1 REPLY 1
Logan Wendholt
Associate
Posted on May 05, 2018 at 01:24

It appears that my answer may be in section 12.6 of the STM8L052C6 reference manual:

12.6 External interrupts

Eleven interrupt vectors are dedicated to external Interrupt events:

•

EXTIB/G - 8 lines on Port B or G: PB[7:0] or PG[7:0]EXTID/H - 8 lines on Port D or H:

PD[7:0] or PH[7:0]

•

EXTIE/F - 8 lines on Port E or F: PE[7:0] or PF[7:0]

•

EXTI0 - 6 lines on Port A/B/C/D/E/F, bit 0: Px[0]

•

EXTI1 - 5 lines on Port A/B/C/D/E, bit 1: Px[1]

•

EXTI2 - 5 lines on Port A/B/C/D/E, bit 2: Px[2]

•

EXTI3 - 5 lines on Port A/B/C/D/E, bit 3: Px[3]

•

EXTI4 - 5 lines on Port A/B/C/D/E, bit 4: Px[4]

•

EXTI5 - 5 lines on Port A/B/C/D/E, bit 5: Px[5]

•

EXTI6 - 5 lines on Port A/B/C/D/E, bit 6: Px[6]

•

EXTI7 - 5 lines on Port A/B/C/D/E, bit 7: Px[7]

So it appears that I would use EXTI0 for PC0, EXTI1 for PC1, etc. and the ambiguity of using EXTIB/G and EXTID/H instead of EXTIB and EXTID is intentional so that the same documentation can apply to all chips in the STM8L052 family.

In this case, it appears that there is no error in the datasheet, just some ambiguity that requires careful inspection to clarify. Apologies for the false alarm.