Erratum ''Unexpected DIV/DIVW instruction result in ISR'' - is only the first division affected??
Posted on July 19, 2015 at 21:03According to the erratum in the title, bit 6 of register cc should be reset at the start of an ISR. The erratum note provides code examples for workarounds. Apparently the result of div/divw is wrong when bit 6 of cc ...