Posted on July 19, 2015 at 21:03According to the erratum in the title, bit 6 of register cc should be reset at the start of an ISR. The erratum note provides code examples for workarounds.
Apparently the result of div/divw is wrong when bit 6 of cc is set before the instruction. And bit 6 is set and reset by the instruction while it is executed.
So I guess bit 6 is always reset after div/divw, an thus only the very fist div/divw in the isr gives a potentially wrong result?
Philipp
