2025-12-15 5:59 AM - last edited on 2025-12-15 6:33 AM by mƎALLEm
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Hi,
I was trying to use multiple ADCs in stm32f103c8t6. I have configured seven channels in ADC1 using DMA and ADC2 as single channel without DMA. Both trigger interrupts where ADC2 has the highest priority.
The sampling time for the seven channels of ADC1 and single channel of ADC2 is 41.5 cycles and 239.5 cycles respectively.
The ADC clock frequency is 10.667MHz. I calculate that ADC1 interrupt is triggered every 35.4us and ADC2 interrupt is triggered every 23.6us.
System clock is 64Mhz.
I have a third Interrupt which is a timer interrupt which is triggered every 560us.
So the problem now is that when the sampling time of ADC2 is reduced 71.5 cycles (approx 8 us) or below, only the ADC2 is getting triggered. The code is not triggering the ADC1 interrupt and/or the timer interrupt.
Is there any limit to interrupt frequency in STM32F103 or am I doing something wrong here?
Here is a snippet of the code :-
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
if(hadc->Instance == ADC1)
{
HAL_GPIO_WritePin(GPIOC,GPIO_PIN_13,SET);
raw_adc[0] = buffer[0];
raw_adc[1] = buffer[1];
raw_adc[2] = buffer[2];
raw_adc[3] = buffer[3];
raw_adc[4] = buffer[4];
raw_adc[5] = buffer[5];
raw_adc[6] = buffer[6];
raw_adc[7] = buffer[7];
HAL_GPIO_WritePin(GPIOC,GPIO_PIN_13,RESET);
}
if(hadc->Instance == ADC2)
{
adc_val = HAL_ADC_GetValue(&hadc2);
}
}
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef* htim)
{
if(htim->Instance == TIM4)
{
HAL_GPIO_WritePin(GPIOC,GPIO_PIN_15,SET);
.
.
.
.
}
}
2025-12-15 6:27 AM
The interrupt frequency is not directly limited, but code takes time to execute and the cpu will only be able to run so many instructions per second.
If your interrupts do not finish before the next interrupt occurs, that will lead to code not being executed as often as you'd like.
Generally, expect interrupt frequency to be limited to tens of kHz. More optimized code can push this higher. HAL is optimized for flexibility, not speed.