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Comparing Nucleo-H743ZI2 and Nucleo-H745ZI-Q

CMcSh.1
Associate II

I've written some code in STM32CubeIDE for the Nucleo-H743 which is simply toggling the board's LEDs and using the SPI channels to tx/rx with a few A/D converters. I've measured the loop's time to execute with a scope to be ~20us.

I also have a Nucleo-H745 and set up the M7 core (since this is dual core) with the same code, paying close attention to the clock setup ensuring the speeds for the core and the peripherals all matched the H743 board's setup. Running that same code, I see a loop time of ~150us.

From a high level point of view, the M7 core for each of these boards look to have the same capabilities so I would expect a closer match which is obviously not the case. Double checking the compiler was configured the same for both projects, I'm at a loss why there is such a difference.

6 REPLIES 6

7.5x slower, probably the cache, or it's running off the 64 MHz HSI because other clocks aren't starting.

Print out the SystemCoreClock, and perhaps thos of AHB, APB1, APB2, etc.

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CMcSh.1
Associate II

Hi Tesla DeLorean, here are two snips from the clock config.

This is the H743:

0693W00000Y6wnTQAR.jpg 

And the H745:

0693W00000Y6wmLQAR.jpg 

The main difference I can see is the HSE crystal being different between these two boards which requires adjusting the PLLs differently to achieve the same clock speeds. I did attempt using the CSI and HSI input to the PLLs and found it to be unstable when setting the sysclk up to 480.

Well if it achieved that it wouldn't be running 7.5x slower. The best explanation I have, is that it is not.

Unpack the RCC/PLL settings at the point where you make the time measurement.

 printf("HCLK=%9d\n", HAL_RCC_GetHCLKFreq());

 printf("APB1=%9d\n", HAL_RCC_GetPCLK1Freq());

 printf("APB2=%9d\n", HAL_RCC_GetPCLK2Freq());

If the part is running unstably at speed I'd look at the VCAP pins and the VOS settings.

Make sure HSE_VALUE reflects board expectations.

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CMcSh.1
Associate II

HSE_VALUE looks correct for both.

H743:

0693W00000Y6x87QAB.pngH745:

0693W00000Y6x8HQAR.png 

The freq return functions gave me unexpected results however.

H743:

0693W00000Y6x8qQAB.jpgH745:

0693W00000Y6x8vQAB.jpg 

This result is confusing. So, the H743 is running faster than it should be, and stable? I was quite happy with the ~20us. :sad_but_relieved_face:

Looking for the why, I've verified the PLL values are configured as seen in the graphical clock tool.

H743:

  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 1;
  RCC_OscInitStruct.PLL.PLLN = 120;
  RCC_OscInitStruct.PLL.PLLP = 2;
  RCC_OscInitStruct.PLL.PLLQ = 8;
  RCC_OscInitStruct.PLL.PLLR = 8;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  RCC_OscInitStruct.PLL.PLLFRACN = 0;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }
 
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }

And H745:

  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 5;
  RCC_OscInitStruct.PLL.PLLN = 192;
  RCC_OscInitStruct.PLL.PLLP = 2;
  RCC_OscInitStruct.PLL.PLLQ = 8;
  RCC_OscInitStruct.PLL.PLLR = 10;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  RCC_OscInitStruct.PLL.PLLFRACN = 0;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }
 
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }

Are they using crystals, or TCXO sources?

If crystals, don't use BYPASS

HSI based, something along the lines of this..

static void SystemClock_Config(void)
{
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 
//..
 
  /* Enable HSI Oscillator and activate PLL with HSI as source */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON; // 64 MHz
  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
  RCC_OscInitStruct.CSICalibrationValue  = RCC_CSICALIBRATION_DEFAULT;
 
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 
  RCC_OscInitStruct.PLL.PLLM = HSI_VALUE / 8000000; //  8 MHz fCOMP
  RCC_OscInitStruct.PLL.PLLN = 120; // 8x120 = 960
 
  RCC_OscInitStruct.PLL.PLLP = 2;
  RCC_OscInitStruct.PLL.PLLR = 8;
  RCC_OscInitStruct.PLL.PLLQ = 8;
 
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
  RCC_OscInitStruct.PLL.PLLFRACN  = 0;
 
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler(__FILE__, __LINE__);
  }
 
/* Select PLL as system clock source and configure  bus clocks dividers */
  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 
              RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
 
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler(__FILE__, __LINE__);
  }
 
//...
}

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CMcSh.1
Associate II

These are crystals. I've changed the HSE source to crystal/ceramic as well as tried working with something similar to your HSI setup above. After a few iterations there is some progress.

As it stands now - both H743 and H745 boards are set up with HSE, and both boards return the same frequencies with the HAL_RCC_Get clock functions:

0693W00000Y70jGQAR.png 

This looks like a big step in the right direction, going back to the scope and the same main loop code both boards show improvement although still more variance than I would expect.

H743: ~16us total loop time

H745: ~56us total loop time