cancel
Showing results for 
Search instead for 
Did you mean: 

The new ANA0 / ANA1 pins

Bumsik Kim
Senior

0690X000009Ymq4QAC.png

Hi,

I'm currently figuring out about the new ANA0 / ANA1 pins.

As far as I understand, those pins are always connected to the ADC so that I don't need to touch the GPIO registers in order to use those pins. Is my understanding correct?

Also I can connect those pin to PA0 / PA1 using ANAx_SEL bits in SYSCFG_PMCR register. In this case is it possible to short or damage the circuit/chip when I set different signal between ANAx and PAx?

Thanks a lot!

1 ACCEPTED SOLUTION

Accepted Solutions
PatrickF
ST Employee

Your understanding about ANA0/ANA1 is correct, they are always connected to ADC to avoid to go thru an analog switch (which is the case for all other ADC inputs, which due to its resistivity, could limit ADC sampling capacitor minimum charge time.

There is no need to any GPIO settings to use ANAx (obvious as not linked to a GPIO).

The ANAx_SEL are there for legacy usage, I did not see any rationale to use it in most cases (as there is as well other ADC inputs on PAx).

Yes, there is a small risk of damage, e.g. if you externally drive voltage on ANA0/ANA1 with low impedance and at same time driving PA0/PA1 in output or input while the 'switch' between ANAx/PAx is closed using ANAx_SEL.

Major concern of uncontrolled usage of IOs is current leakage in your system.

As a general rule, risk is there whenever the limit values in datasheet are not respected (i.e. injected current, input voltages, etc..). Otherwise, IOs are quite robusts and tolerant to most misuses.

So, to avoid issue, in case ANAx_SEL=1 is used, ANAx pin must be left open in the system.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

View solution in original post

4 REPLIES 4
Uwe Bonnes
Principal II

What chip are you talking about?

I'm talking about STM32MP157x, and possibly all STM32 MPU series.

PatrickF
ST Employee

Your understanding about ANA0/ANA1 is correct, they are always connected to ADC to avoid to go thru an analog switch (which is the case for all other ADC inputs, which due to its resistivity, could limit ADC sampling capacitor minimum charge time.

There is no need to any GPIO settings to use ANAx (obvious as not linked to a GPIO).

The ANAx_SEL are there for legacy usage, I did not see any rationale to use it in most cases (as there is as well other ADC inputs on PAx).

Yes, there is a small risk of damage, e.g. if you externally drive voltage on ANA0/ANA1 with low impedance and at same time driving PA0/PA1 in output or input while the 'switch' between ANAx/PAx is closed using ANAx_SEL.

Major concern of uncontrolled usage of IOs is current leakage in your system.

As a general rule, risk is there whenever the limit values in datasheet are not respected (i.e. injected current, input voltages, etc..). Otherwise, IOs are quite robusts and tolerant to most misuses.

So, to avoid issue, in case ANAx_SEL=1 is used, ANAx pin must be left open in the system.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

Well explained, thanks!