STM32MP157C with MII PHY not working, attempt 2

[BillR]

Same situation as before - using a STM32MP157C based design + KSZ9021GN PHY but now actually wired for MII mode.

Previous board was wired for GMII mode, even verified by Microchip/Micrel, not realizing the MPU did not support that mode (should have checked with CubeMX!) .

So, we made the change to actually MII wiring into a different but similar board being designed at the time. That board is now being brought up.

Again, PHY issue, but different this time and I hope its not another design error. I suppose there could be an assembly problem of course. I only have one board currently to test.

Here is the TL;DR of the bootup relating to ethernet. Note "device missing", and we are at address 3.

...
[ 2.510008] stm32-dwmac 5800a000.ethernet: PTP uses main clock
[    2.514391] stm32-dwmac 5800a000.ethernet: no reset control found
[    2.520607] stm32-dwmac 5800a000.ethernet: No phy clock provided...
[    2.527384] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42
[    2.533753] stm32-dwmac 5800a000.ethernet:   DWMAC4/5
[    2.538686] stm32-dwmac 5800a000.ethernet: DMA HW capability register supported
[    2.545949] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine supported
[    2.553278] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported
[    2.560142] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported
[    2.566380] stm32-dwmac 5800a000.ethernet: TSO supported
[    2.571709] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    2.579545] stm32-dwmac 5800a000.ethernet: device MAC address ce:23:29:68:f0:bb
[    2.586815] stm32-dwmac 5800a000.ethernet: TSO feature enabled
[    2.592947] libphy: stmmac: probed
[    2.596331] mdio_bus stmmac-0: MDIO device at address 3 is missing.
...

...
[   11.439910] stm32-dwmac 5800a000.ethernet eth0: no phy at addr -1
[   11.444566] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Cannot attach to PHY (error: -19)
...

I've gone over the device tree and I believe the pin mapping is correct, and here's this:

 
&ethernet0{
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&eth1_pins_mx>;
	pinctrl-1 = <&eth1_sleep_pins_mx>;
	status = "okay";
 
	/* USER CODE BEGIN ethernet0 */
        st,eth_clk_sel = <1>;
        phy-mode = "mii"; 
	max-speed = <100>; 
	phy-handle = <&phy0>;
 
	mdio0 { 
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <3>; 
		};
	};
	/* USER CODE END ethernet0 */
};
 
 

Thanks again for any ideas, BillR

[BillR]

Initially I thought the boot log indicated that it was at least talking to the PHY over MDIO, but then realized its just not seeing the PHY at all. Will be probing some hardware next week and try another board when they come in.

[BillR · Accepted solution]

All set now, it works. 🙂

C8 was supposed to be 10uF, rather than 0.1uF for the proper reset timing.