STM32MP157 USBOTG core register GRSTCTL_CSFTRST is not auto-clearing itself

[ZUl A.1]

I am trying to use the USB OTG in host mode, but it kept giving me the famous HANG! Soft Reset timeout GRSTCTL_CSFTRST error.

According to the datasheet, when we set the register, it should reset the core but also clear itself but the following condition checks if it is 0 or not.

	if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
		(DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
		if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
					      GRSTCTL_CSFTRST, 10000)) {
			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
				 __func__);
			return -EBUSY;
		}

Here is some debugging that I have done

GRSTCTL VALUE before reset: 0x80000400

GRSTCTL VALUE after reset: 0x80000401

GRSTCTL inside if condition: 0x80000001

Here you can see, it has even cleared the 10th bit itself but did not clear the bit 0.

Following is my device tree, I still consider myself a beginner, so I need help.

&usbotg_hs{
	u-boot,dm-pre-reloc;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&usbotg_hs_pins_a &usbotg_fs_dp_dm_pins_a>;
	status = "okay";
 
	/* USER CODE BEGIN usbotg_hs */
	
	compatible = "st,stm32mp15-fsotg", "snps,dwc2"; /* Use full-speed integrated PHY */
	
	vbus-supply = <&vbus_otg>;                      /* voltage regulator to supply Vbus */
	
	reg = <0x49000000 0x10000>;
	clocks = <&rcc USBO_K>;
	clock-names = "otg";
	resets = <&rcc USBO_R>;
	reset-names = "dwc2";
	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	dr_mode = "otg";
	//dr_mode = "peripheral";
	g-rx-fifo-size = <256>;
	g-np-tx-fifo-size = <32>;
	g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
	maximum-speed = "full-speed";
	phy_type = "serial";
	
	/* USER CODE END usbotg_hs */
};

If I am not setting the clock correctly, let's assume I should not get any value when I read any register, while I do get the value when I try to read any register.