Access Tampers and BckSRAM from M4.

[AGamb.4]

Hello,

Is there a way to access the Tamper or backup registers or the backup sram from the MCU? Or is it physically imposible to do so?

Edit:

I am still looking for an answer, I just saw in the RCC registers that I can enable BKPSRAM bits to:

• enable the peripheral for MP (RCC_MP_AHB5ENSETR) and MC (RCC_MC_AHB5ENSETR)
• enable the peripheral for MP (RCC_MP_AHB5LPENSETR) and MC (RCC_MC_AHB5LPENSETR) in low power

Does this mean the MCU is able to access the BKPSRAM peripheral?

Although I do not see a clock enable for the TAMP, is it the same for the tamper (and backup registers)?

Best regards,

Andrés

[Olivier GALLIEN]

Hi @AGamb.4​ ,

m4 can access tamper and Bckpsram but it require to set those as non-secure and this can have important impact on Linux features.

See the warning banner here :

https://wiki.st.com/stm32mpu/wiki/BKPSRAM_internal_memory#Overview

Olivier

[AGamb.4]

Hello @Community member​ 

Thanks for the answer, I made a test and can confirm the M4 has access to the tamper, did not test the bkpsram though.

The wiki (https://wiki.st.com/stm32mpu/wiki/STM32MP15_peripherals_overview) is misleading in this aspect, as it indicates the tamper is only shared between A7S and A7NS. The BKPSRAM is indicated to be allocable to one or the other.

But it is not mentioned this peripherals are accessible from the M4. Is this a general rule? Are all the peripherals allocated to A7NS accessible from the M4?

Best regards,

Andrés

[Olivier GALLIEN · Accepted solution]

Hi @AGamb.4​ ,

Not a general rules, rather a case by case.

Actually wiki page you mention is and remains the reference for what ST is supporting from SW ecosystem point of view.

Usage of BKPSRAM from M4 is in a kind of grey zone.

Possible from HW point of view, but not seen as a major use case to be supported by default in our offer.

And now, since it prevent to use some default OSTL feature such as Low power we prefer to not promote it.

Hope it's clear.

Olivier

[AGamb.4]

Hello Olivier,

Thank you for the information.

I am asking these questions because we might use the processor for our projects and we need to know what can be done and what can not in order to use it in the safest and most secure way possible. Our use cases are not major ones but we would like to use this MPU, is there more detailed documentation than the reference manual?

Can I assume any peripheral that can be allocated to the Non-Secured world (shared or not) can also be accessed from the MCU? From the reference manual (chapter "15.6 MCU Resource Isolation") and your response I get to the conclusion that I can assume so, could you confirm it?

There is no capacity to isolate a peripheral only to the A7, right? I mean, accessible from Cortex A7 Secure and Non secure but not accesible from the Cortex M4.

Best regards,

Andres