STM32MP1 CM4 SRAM cleared after WWDG reset

[Jagr]

Hi,

i want to store some flags, bytes, at the end of my SRAM. This RAM section should preserve the information in case of a Reset e.g. WWDG1 Reset.
Before WWDG1 Reset is executed some program states should be stored in RAM and after Reset could be read out to get more information about what happend.

I defined the section in RAM as follows:

/* Memories definition */
MEMORY
{
  RETRAM_interrupts (RX)	: ORIGIN = 0x00000000, LENGTH = 32k
  m_ipc_shm    	 (RW)	: ORIGIN = 0x38008000, LENGTH = 32K
  SRAM1_FLASH       (RX)	: ORIGIN = 0x10000000, LENGTH = 192K
  SRAM2_RAM         (RWX) : ORIGIN = 0x10030000, LENGTH = (192K - 256)
  FLAGS		     (RW)	: ORIGIN = 0x1005FF00, LENGTH = 256
}
...

.noinit (NOLOAD):
  {
     KEEP(*(.FlagSection)) 	/* keep my variable even if not referenced */
  } > FLAGS

Accessed by declaring array

uint8_t flag_buf[256] __attribute__((section (".FlagSection")));

I can move the information to flag_buf[] as desired and its there until a WWDG1 reset occurs.
After CM4 firmware starts again the FLAGS sections seems to be cleared and full of 0x00.

I thought with `NOLOAD` the section remains untouched?!

Does anybody did something like that or has a good advise.

Thanks

Regards

Jan

[Olivier GALLIEN]

Hi @Jagr 

In which boot mode are you ? Production or engineering ? 

Please check that WWDG1 is configured only for a local reset (CM4) and not platform reset ( then power cycle of plateform cutting SRAM power) 

Olivier 

[Jagr]

Good Morning,

most of the time i run the controller in Production Mode but i am prettya sure that i have the same behaviour in Engineer Mode too.
The A7 firmware does not reset if WWDG1 reset occurs and i do not set the OTP_MCU_SYSRST_EN bit
additional i cannot see a toggle at NRST Pad.

So i think WWDG1 should only reset CM4 Core.

Jan