cancel
Showing results for 
Search instead for 
Did you mean: 

STM32MP1 - I2C frequency too low

Dat Tran
Senior II

In my device tree, we config 400KHz, but on scope we see only ~ 50Hz, and the clock seems weird. Anyone know why?

&i2c1 {

pinctrl-names = "default", "sleep";

pinctrl-0 = <&i2c1_pins_a>;

pinctrl-1 = <&i2c1_sleep_pins_a>;

i2c-scl-rising-time-ns = <185>;

i2c-scl-falling-time-ns = <20>;

clock-frequency = <400000>;

status = "okay";

/delete-property/dmas;

/delete-property/dma-names;

};


_legacyfs_online_stmicro_images_0693W00000bjEZXQA2.png

1 ACCEPTED SOLUTION

Accepted Solutions
PatrickF
ST Employee

Hi @Community member​ 

I confirm both I2C pins should be open-drain (I2C standard to allow clock stretching and acknowledge) with pull-ups.

I think you miss pull-ups on your board (we put 1.5K on our boards).

Internal pull-up might work, but rising time will be quite bad and could create timing issues even at 400kHz if your bus is loaded by multiple devices and/or long wires.

Regards,

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

View solution in original post

4 REPLIES 4
Erwan SZYMANSKI
ST Employee

Hello @Community member​ ,

What board do you use ? A custom board ? A discovery board ? MP15 / MP13 ?

Can you check the output of "cat /sys/kernel/debug/clk/clk_summary" and share the ouput of this command ?

The driver i2c-stm32f7.c used to control I2C has dynamic debug available (dev_dbg). Can you activate it or replace dev_dbg by dev_info just to check traces inside the driver at boot / probe time ?

Kind regards,

Erwan.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
Dat Tran
Senior II

Hi, Thanks Erwan,

We use custom board, MP151AAC3 MCU.

We did a bit more investigation and found that 'drive-open-drain' causes this issue. When we temporary remove this line in device tree see that the clock is 400KHz as well.

But when we remove drive-open-drain then I2c transaction failed, but the clock on scop looks correctly.

Do you have any idea why when add drive-open-drain the clock become weird?

&pinctrl {

i2c1_pins_a: i2c1-0 {

pins {

pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */

<STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */

bias-disable;

drive-open-drain; /*Remove this line will make good clocking */

slew-rate = <0>;

};

};

};


_legacyfs_online_stmicro_images_0693W00000bjJ0rQAE.png

Dat Tran
Senior II

Seem change bias-disable to pull up everything work well


_legacyfs_online_stmicro_images_0693W00000bjJ1HQAU.png

PatrickF
ST Employee

Hi @Community member​ 

I confirm both I2C pins should be open-drain (I2C standard to allow clock stretching and acknowledge) with pull-ups.

I think you miss pull-ups on your board (we put 1.5K on our boards).

Internal pull-up might work, but rising time will be quite bad and could create timing issues even at 400kHz if your bus is loaded by multiple devices and/or long wires.

Regards,

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.