PLL4 Clock Exception and Ethernet issue

[Louis1]

Hi,

I'm getting an exception stack on bootup:

[ 3.882380] ------------[ cut here ]------------
[ 3.886351] WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:969 clk_core_disable+0xf0/0x2c4
[ 3.894281] pll4_p already disabled
[ 3.897839] Modules linked in:
[ 3.900798] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 5.15.145 #1
[ 3.908314] Hardware name: STM32 (Device Tree Support)
[ 3.913395] [<c0110c4c>] (unwind_backtrace) from [<c010c668>] (show_stack+0x10/0x14)
[ 3.921128] [<c010c668>] (show_stack) from [<c0c697e8>] (dump_stack_lvl+0x40/0x4c)
[ 3.928753] [<c0c697e8>] (dump_stack_lvl) from [<c0125888>] (__warn+0x88/0x128)
[ 3.935978] [<c0125888>] (__warn) from [<c0c63c94>] (warn_slowpath_fmt+0x78/0xa8)
[ 3.943510] [<c0c63c94>] (warn_slowpath_fmt) from [<c0696480>] (clk_core_disable+0xf0/0x2c4)
[ 3.951849] [<c0696480>] (clk_core_disable) from [<c0c6a298>] (clk_core_disable_lock+0x18/0x24)
[ 3.960589] [<c0c6a298>] (clk_core_disable_lock) from [<c1120fc8>] (clk_disable_unused_subtree+0x21c/0x228)
[ 3.970345] [<c1120fc8>] (clk_disable_unused_subtree) from [<c1120de4>] (clk_disable_unused_subtree+0x38/0x228)
[ 3.980404] [<c1120de4>] (clk_disable_unused_subtree) from [<c1120de4>] (clk_disable_unused_subtree+0x38/0x228)
[ 3.990462] [<c1120de4>] (clk_disable_unused_subtree) from [<c1120de4>] (clk_disable_unused_subtree+0x38/0x228)
[ 4.000520] [<c1120de4>] (clk_disable_unused_subtree) from [<c112102c>] (clk_disable_unused+0x58/0xf8)
[ 4.009768] [<c112102c>] (clk_disable_unused) from [<c01021f8>] (do_one_initcall+0x54/0x2a4)
[ 4.018208] [<c01021f8>] (do_one_initcall) from [<c110149c>] (kernel_init_freeable+0x250/0x2bc)
[ 4.026956] [<c110149c>] (kernel_init_freeable) from [<c0c76048>] (kernel_init+0x10/0x128)
[ 4.035199] [<c0c76048>] (kernel_init) from [<c0100134>] (ret_from_fork+0x14/0x20)
[ 4.042728] Exception stack(0xc189ffb0 to 0xc189fff8)
[ 4.047712] ffa0: 00000000 00000000 00000000 00000000
[ 4.055937] ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 4.064060] ffe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 4.070655] ---[ end trace ccb0495ae3f1d280 ]---

And then later on I get the following:

[ 12.101593] stm32-dwmac 5800a000.ethernet eth0: PHY [stmmac-0:03] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)
[ 12.115767] stm32-dwmac 5800a000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[ 13.139498] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[ 13.144339] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 13.169541] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed

I am guessing the second dump is due to the first dump. I have PLL4P configured in my CubeMX to provide a 125 MHz clock to ETH. My ethernet device tree is configured as:

&ethernet0{
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth1_pins_mx>;
pinctrl-1 = <&eth1_sleep_pins_mx>;
status = "okay";

/* USER CODE BEGIN ethernet0 */
    phy-mode = "rgmii-id";
    max-speed = <1000>;
    phy-handle = <&phy0>;
    st,eth-clk-sel;
    clock-names = "stmmaceth",
                  "mac-clk-tx",
                  "mac-clk-rx",
                  "eth-ck",
                  "ethstp";
    clocks = <&rcc ETHMAC>,
             <&rcc ETHTX>,
             <&rcc ETHRX>,
             <&rcc ETHCK_K>,
             <&rcc ETHSTP>;
    mdio0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "snps,dwmac-mdio";
        phy0: ethernet-phy@3 {
            compatible = "ethernet-phy-ieee802.3-c22";
            reg = <3>;
            reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
        };
    };
/* USER CODE END ethernet0 */
};

Also my PLL4 in TF-A and Optee device trees are configured as:

pll4:st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 1 61 5 8 5 PQR(1,0,1) >;
frac = < 0x1000 >;
};

And I have CLK_ETH_PLL4P set in TF-A and Optee.

Any help would be greatly appreciated!!