BL32 does not start

[kiichi]

Custom STM32MP151A board with 512MB DDR2.

I am trying to write via UART communication with STM32CubeProgrammer, but BL32 processing does not start.

What should I do to investigate the cause?

[2024-01-12 14:11:52.591] NOTICE: CPU: STM32MP151AAC Rev.Z
[2024-01-12 14:11:52.591] NOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-5.15-yocto-kirkstone-mp1-v22.11.23
[2024-01-12 14:11:52.623] INFO: PMIC version = 0x21
[2024-01-12 14:11:52.623] WARNING: VDD unknown
[2024-01-12 14:11:52.623] INFO: Reset reason (0x14):
[2024-01-12 14:11:52.696] INFO: Pad Reset from NRST
[2024-01-12 14:11:52.696] INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe2000
[2024-01-12 14:11:52.696] INFO: FCONF: Reading firmware configuration information for: stm32mp_io
[2024-01-12 14:11:52.696] INFO: Using UART
[2024-01-12 14:11:52.696] INFO: Instance 8
[2024-01-12 14:11:52.696] INFO: Boot used partition fsbl1
[2024-01-12 14:11:52.696] NOTICE: BL2: v2.6-stm32mp1-r2.0(debug):v2.6-dirty(a1f02f4f)
[2024-01-12 14:11:52.696] NOTICE: BL2: Built : 13:14:26, Nov 23 2021
[2024-01-12 14:11:52.696] INFO: BL2: Doing platform setup
[2024-01-12 14:11:52.696] INFO: RAM: LPDDR2 32bits 360000kHz
[2024-01-12 14:11:52.696] INFO: Memory size = 0x20000000 (512 MB)
[2024-01-12 14:11:52.711] INFO: UART: read phase 3 at 0xc7000000 size 0x1000000
[2024-01-12 14:13:19.102] WARNING: UART: Bad packet number receive: 13500416, expected 1331
[2024-01-12 14:14:04.514] WARNING: UART: Bad packet number receive: 13500416, expected 2039
[2024-01-12 14:16:39.908] INFO: UART: Start phase 3
[2024-01-12 14:16:40.047] INFO: BL2: Loading image id 1
[2024-01-12 14:16:40.047] INFO: Loading image id=1 at address 0x2ffff000
[2024-01-12 14:16:40.047] INFO: Image id=1 loaded: 0x2ffff000 - 0x2ffff226
[2024-01-12 14:16:40.047] INFO: FCONF: Reading FW_CONFIG firmware configuration file from: 0x2ffff000
[2024-01-12 14:16:40.047] INFO: FCONF: Reading firmware configuration information for: dyn_cfg
[2024-01-12 14:16:40.047] INFO: FCONF: Reading firmware configuration information for: stm32mp1_firewall
[2024-01-12 14:16:40.047] INFO: BL2: Loading image id 4
[2024-01-12 14:16:40.047] INFO: Loading image id=4 at address 0x2ffc5000
[2024-01-12 14:16:40.047] INFO: Image id=4 loaded: 0x2ffc5000 - 0x2ffd9820
[2024-01-12 14:16:40.047] INFO: BL2: Skip loading image id 8
[2024-01-12 14:16:40.047] INFO: BL2: Skip loading image id 9
[2024-01-12 14:16:40.047] INFO: BL2: Loading image id 2
[2024-01-12 14:16:40.047] INFO: Loading image id=2 at address 0xc0500000
[2024-01-12 14:16:40.047] INFO: Image id=2 loaded: 0xc0500000 - 0xc0511688
[2024-01-12 14:16:40.047] INFO: BL2: Loading image id 16
[2024-01-12 14:16:40.047] INFO: Loading image id=16 at address 0x2ffc0000
[2024-01-12 14:16:40.047] INFO: Image id=16 loaded: 0x2ffc0000 - 0x2ffc4039
[2024-01-12 14:16:40.047] INFO: BL2: Loading image id 5
[2024-01-12 14:16:40.047] INFO: Loading image id=5 at address 0xc0100000
[2024-01-12 14:16:40.047] INFO: Image id=5 loaded: 0xc0100000 - 0xc01ece88
[2024-01-12 14:16:40.048] NOTICE: BL2: Booting BL32
[2024-01-12 14:16:40.048] INFO: Entry point address = 0x2ffc5000
[2024-01-12 14:16:40.048] INFO: SPSR = 0x1d3
[2024-01-12 14:16:40.284] PANIC at PC : 0x2ffc98b1
[2024-01-12 14:16:40.284]
[2024-01-12 14:16:40.284] Exception mode=0x00000016 at: 0x2ffc98b1

[kiichi]

Thank you for your reply

I reviewed the DDR settings, but it didn't seem to be the cause of the problem.

I have a question.

In the case of EV1, [U-Boot] is output 65ms after [SP_MIN:] is output.

->EV1_console.log

However, in the case of custom board, [ ERROR: Illegal access to 0xe0000000: ] is output after 4 seconds after [ SP_MIN: ] is output.

->custum_board_console.log

The Boot sequence is recognized as below.

  ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot)

Do you think [ ERROR: Illegal access to 0xe0000000: ] occurs in BL32?

Or do you think it occurs with BL33 (U-Boot)?

Thank you very much for letting me know.

[kiichi]

hi @PatrikF

I am checking the transition from BL32 (SP_min) to BL33 (U-Boot).

  BL32 (SP_min) -> BL33 (U-Boot)

I confirmed that the sp_min_main() function finishes.
I also confirmed that 0xc0500000 was written in the smc_ctx_t table.

(0xc0500000 was written in this table on the EV1 board as well.)
I would like to know what process (function name, etc.) to move to after this.

I would like to know what kind of processing (function name, etc.) will proceed after this, so please let me know.

Thx

Kiich

[kiichi]

hi @PatrikF

Our custom board is STM32MP151A board with 512MB DDR2.

I thought that I should change the STM32MP_DDR_MAX_SIZE below to 512MB.
    /* DDR configuration */
    #define STM32MP_DDR_BASE U(0xC0000000)
    #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */　<<--

however
I changed STM32MP_DDR_MAX_SIZE to 512MB and ran it.
Then, the xlat_tables_map_region() function in the xlat_tables_core.c file has the expected value.
It did not return the value (0xc0000000+0x20000000-1).
It returned 0xc0000000 and ended abnormally.

question
Should STM32MP_DDR_MAX_SIZE be 1GB regardless of the DDR size?

Kiichi

[Badzonor]

Hello, did you resolve the issue? I Have similar problem as my boot fails after booting BL32 but ends with 

Data Abort at: 0x2ffcd056 DFSR = 0x00000206 DFAR = 0x00000000

I have tested my DDR via SWD and it is working.

Thanks, Dominik

[kiichi]

The problem was solved by deleting "vtt_ddr" from the PMIC setting in the OPTEE device tree.

Thanks

Kiichi

[DMårt]

@kiichi 

How can you even boot if you're missing vtt_ddr?

Sounds weird, because when I missed vtt_ddr, then I could not boot the first .stm32 file in CubeProg

[Badzonor]

Hello, we managed to get further by switching from SP_min to OPTEE and now we have similar issue with dt_get_cpu_regulator(). You attached .dts mentioned that you solved the issue but it is hard to know that you changed when we don't have previous .dts file. Can you tell us what change resolved the issue?

Thank you, Dominik.

[kiichi]

"vtt_ddr" in the TFA device tree has been left as is, but "vtt_ddr" in the OPTEE device tree has been deleted.

　/*
　* vtt_ddr:ldo3{
　* regulator-name = "vtt_ddr";

　*/

[Badzonor]

Hello, I tried that, in my case ldo3 is ddr_vdd1 as I use LPDDR3 but nothing changed so far. We will keep trying.

Thank you!

[kiichi]

I added optee_framebuffer@dd000000 to the U-BOOT device tree.

I hope this helps.

reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;

/* USER CODE BEGIN reserved-memory */

optee_framebuffer@dd000000 {
reg = <0xdd000000 0x01000000>;
no-map;
};

optee@de000000 {
reg = <0xde000000 0x02000000>;
no-map;
};

/* USER CODE END reserved-memory */
};