Introduction to CK_INT clock
The STM32 products include a flexible clock system for timers, enabling each timer to operate with a specific kernel clock. The RCC configuration determines the kernel clock source for each timer.
Timers can utilize various clock sources, such as PLLs, HSI, LSE, or other system clocks, depending on the timer type and configuration. The actual timer clock frequency depends on the APB prescaler settings and the TIMPRE bit in the RCC_CFGR register.
1. STM32H7 timers
Timer connections with APB differ from one product to another, however, the information is always detailed in the product datasheet, typically within the block diagram. In this section, we focus on the STM32H7 series.
This is the STM32H7B0xB block diagram, showcasing different timer connections:
- TIM1 and TIM8 (advanced timers) are connected to APB2.
- TIM15, TIM16, and TIM17 are also connected to APB2.
- All other timers, including general-purpose and basic timers, are connected to APB1.
This bus allocation impacts the timers’ clock sources and their maximum operating frequencies, which are critical for designing precise timing and control applications.
You can find this information presented in a table format in the following community post titled "What is the internal clock CK_INT for the STM32H7 timers?", contributed by our community member @Intector .
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2. Timer clock calculation
The following figure shows a simplified view of the clock distribution for the CPU and busses:
This table is taken from RM0455
This block provides the clock for the timers (rcc_timx_ker_ck and rcc_timy_ker_ck). The frequency of the timers clock depends on the APB prescaler corresponding to the bus to which the timer is connected, and on the TIMPRE bit.
CDPPRE1/CDPPRE2* |
TIMPRE** |
Frcc_timx_ker_ckFrcc_timy_ker_ck |
Frcc_pclk1Frcc_pclk2 |
Comments |
| 0xx |
0 |
Frcc_hclk1 | Frcc_hclk1 | The timer clock is equal to the bus clock. |
| 100 | 0 | Frcc_hclk1 | Frcc_hclk1 / 2 | The timer clock is twice as fast as the bus clock. |
| 101 | 0 | Frcc_hclk1 / 2 | Frcc_hclk1 / 4 | |
| 110 | 0 | Frcc_hclk1 / 4 | Frcc_hclk1 / 8 | |
| 111 | 0 | Frcc_hclk1 / 8 | Frcc_hclk1 / 16 | |
| 0xx | 1 | Frcc_hclk1 | Frcc_hclk1 | The timer clock is equal to the bus clock. |
| 100 | 1 | Frcc_hclk1 | Frcc_hclk1 / 2 | The timer clock is twice as fast as the bus clock. |
| 101 | 1 | Frcc_hclk1 | Frcc_hclk1 / 4 | The timer clock is 4 times faster than the bus clock. |
| 110 | 1 | Frcc_hclk1 / 2 | Frcc_hclk1 / 8 | |
| 111 | 1 | Frcc_hclk1 / 4 | Frcc_hclk1 / 16 |
*CDPPRE1 and CDPPRE2 belong to RCC CPU domain clock configuration register 2 (RCC_CDCFGR2).
**TIMPRE belongs to RCC clock configuration register (RCC_CFGR).
3. Timer enable/disable and control logic
Timers can be individually enabled or disabled via their respective enable bits in the RCC peripheral clock enable registers.
The timer kernel clock is routed to the timer's prescaler and counter logic, which can be configured for up-counting, down-counting, or center-aligned counting modes. The prescaler allows the input clock to be divided by a programmable factor, providing fine control over the timer's counting speed and period.
4. STM32H5 timers
In the STM32H5 series, the timer clock frequency is determined by the APB prescaler configuration.
There are two cases:
- If the APB prescaler equals 1, the timer clock frequencies are set to the APB domain
frequency. - Otherwise, they are set to twice (×2) the APB domain frequency
