Sysclk frequency not stable on STM32WBA55 and STM32WBA52

[ayeiser]

I have been developing a IMU board based on the STM32WBA52KG.  I'm using STM32CubeIDE 1.15.1 with STM32WPAN firmware 1.30.0.  (I've tried using cubeide 1.16.0 with firmware 1.40.0 but was unable to get the code to compile: see this issue: https://community.st.com/t5/stm32-mcus-wireless/ble-wrap-files-missing-after-cube-generation/m-p/700832)

Despite the fact I have low power mode disabled in STM32WPAN config, it seems as though radio active events cause the sysclk frequency to double and then return to normal.  Attached is a scope trace of Timer 1 PWM output--the timer is nominally 500 Hz at 50% duty cycle (1 ms high and 1ms low).  I've verified that the timers running on different APB clocks stay synchronized to each other so this is happening higher up the clock tree, probably around sysclk.  I've also scoped the the HSE oscillator and verified that it stays at 32 MHz while the PWM frequency changes.

This behavior is present in my WBA52-based board and in the STM32WBA55 nucleo board.  I've attached an ioc file nearly identical to one of the ST BLE examples except with timer 1 outputting a PWM signal.

Is this expected behavior?  It caused a lot of problems getting this board up and running.

[EPASZ.1 · Accepted solution]

On the WBA device, System clock manager STM32CubeWBA: System Clock Manager - stm32mcu is used to control and optimize the clock. The main point is that BLE always needs the precise 32MHz clock while operating but then the example applications are set up to switch to 16MHz by default.

To keep 32MHz even when the radio is not working, you can call e.g. 

scm_setsystemclock(SCM_USER_APP, HSE_32MHZ);

 in app_entry.c after SystemPower_Config();.

[ayeiser]

Thank you!