RNG access after starting BLE stack

[eleventen]

It looks as if the RNG is made unavailable to the M4 when the M0 has booted the BLE stack. This looks to be true because I can initialize and use the RNG before starting the BLE stack. Once I launch C2, the RNG registers read as zeros.

Is this a requirement of the BLE stack? We don't use any of the security features in BLE and it would be much more useful to have access to the RNG from the M4 instead of using the HCI interface. Is there a way to we can retain control of the RNG from the M4?

[eleventen]

There is one other detail that is interesting. When we move the clock selection for the RNG (RCC_CCIPR) to the application main(), before invoking the test function, the C2 captures the HSEM semaphore on the RNG before we are able to fetch *any* data from it. We're using LSE for the RNG timing source.

[eleventen]

Also, FWIW, there are no examples that use CFG_HW_RNG_SEMID. In other words, there are no examples that attempt to share the RNG between the C2 and the application core. Do we know that this sharing works?

[MBess.2]

Sorry to bring up such an old thread but I'm having trouble using both cores accessing RN peripheral with BLE Stack running. Ican use RNG with C1 alone so it seems to me that it is kinda the same issue. Did you manage to work it out?

[MSing.1713]

Good question. Let me check...

I don't know if this was every resolved. I have the test code in the product and it generates data. So, as far as I can tell we have it working. To be fair, though, we don't use the cube, so we are implementing everything at the register level.

The most I can offer is this from my patch:

+    The procedure below is what is recommended by ST in AN5289.  What
+    we've observed is that a) the HSI48 clock is disabled by C2 and b)
+    we don't really need to disable the RNG.  We probably need to make
+    sure that the RNGSEL is left in CLK48 mode before we release the
+    HSEM lock.
+
+    Lock HSEM
+    MX_RNG_Init  ()
+      RCC clock enable AHB3
+      Configure SAI1 to get 48MHz
+      LL_RCC_PLLSAI1_Enable
+      LL_RCC_PLLSAI1_EnableDomain_48M
+      Wait for clock to be ready
+      LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLLSAI1);
+      LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_CLK48);
+    LL_RNG_Enable(RNG);
+      RNG_CR |= RNGEN
+    while ()
+      Generate;
+    HAL_RNG_DeInit
+      Clear RNG CED
+      Clear RNG IE and RNGEN
+    __HAL_RCC_RNG_CLK_DISABLE(); //Switch off RNG clock
+      RCC clock disable AHB3
+    Release HSEM