The LCD refresh rate on H7 slower than F4

[HNguy.21]

I use FMC for both H745ZI and F427ZI. I already configured all cores to run at the same clock (168Mhz), but write buffer to F4 seen faster than in H7.

Anyone can help me solve this issue?

I have included clip at: https://drive.google.com/file/d/15hbrxfL3tDqDHbCWVZ2VlnNXuitq1lUi/view

[K.Ata15]

Hey,

Probably your implementation. The FMC is on the 64 bit AXI switch, if you run your code on the M7 core and use the MDMA should be very fast. The 747 unfortunately requires planning and optimisations according to the system architechture (routing, DMA domains, etc.)

K.

[Tesla DeLorean]

The details in the post are a bit superficial.

I'd expect the external interface to actually be clocking slower than 168 MHz, and further slowed by cycle timings.

Why do they even need to be running at 168 MHz, wouldn't the H747 provide for more optimal speeds/settings. A toggling GPIO might be more instructive measurement of relative timing, and data transfer speed.

What controller does the display have? What exactly are you moving across the interface, and from where?

[HNguy.21]

Thank you for your response, I need to searching more in MDMA as you said.

[HNguy.21]

I config to the same speed in order to see the diff of the LCD rate. Actually, H7 can configure more optimal and I just need it run stable as F4.

My controller is FMC for SRAM, in 8080 series MCU interface.

[Tesla DeLorean]

>>My controller is FMC for SRAM, in 8080 series MCU interface.

Figured as much, but what controller specifically are we talking about? And what are the timings?

Which memory on the H7 side is the source for the data being moved to the FMC/LCD? How exactly is that transfer occurring? MPU settings? Caching, etc?

[HNguy.21]

I use NOR/PSRAM bank 3 which is swap to 0xC0000000 (F4 uses it too). this area already configured in normal memory type, WT, Full Access, and Never Execute.