Hello I have a problem compiling TouchGFX for Keil. My procedure:
1/ Run TouchGFX Designer 4.25
2/ Create New project
3/ Go to tab – By Partners – select board Riverdi STM32 121STM32H7
4/ Click to Create
5/ Add Button ( for example)
6/ Click Generate CODE
7/ Go to project Folder and open ioc file Riverdi_121STM32H7_1_6.ioc STM32CubeMx v6.5
8/ Go to tab Middleware and Software pack Select FreeRTOS M7 Select tab Advanced settings USE_NEWLIB_REENTRAND ← disable !!! ( for keil it must be turned off )
9/ Go to project manager Switch toolchain IDE to MDK keil
10/ Save and Generate CODE
11/ After generate code by STM32CubeMx I'm going back to Touchgfx Designer and click generate code again TouchGfx generate code for keil.
12/ Run project in Keil
13/ Go to Option for target Go to tab OUTPUT
and uncheck Browse information
14/ Project build target
15 / Keil linking problem Not enough information to list image symbols.
Not enough information to list load addresses in the image map.
Finished: 2 information, 0 warning and 81 error messages.
"Riverdi_121STM32H7_1_6_CM7\Riverdi_121STM32H7_1_6_CM7.axf" - 81 Error(s), 0 Warning(s).
Target not created.
Build Time Elapsed: 00:00:14
Can anyone please solve the problem with compiling this Riverdi display for KEIL? Please try to compile a simple project for Riverdi STM32H7 display in MDK KEIL.
Thanks
Hello @mcumake ,
I've tried your project, I think I've found out where the issue is. I have 3 suggestions that we could try:
- 1st suggestion : Edit the file system_stm32h7xx_dualcore_boot_cm4_cm7.c (In Common/Src), remove all and paste this instead :
/** ****************************************************************************** * @file system_stm32h7xx_dualcore_boot_cm4_cm7.c * @author MCD Application Team * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. * This provides system initialization template function is case of * an application using a dual core STM32H7 device where * Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes * * This file provides two functions and one global variable to be called from * user application: * - ExitRun0Mode(): Specifies the Power Supply source. This function is * called at startup just after reset and before the call * of SystemInit(). This call is made inside * the "startup_stm32h7xx.s" file. * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. * * - SystemCoreClock variable: Contains the core clock, it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * ****************************************************************************** * @attention * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32h7xx_system * @{ */ /** @addtogroup STM32H7xx_System_Private_Includes * @{ */ #include "stm32h7xx.h" #include <math.h> #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (CSI_VALUE) #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @} */ /** @addtogroup STM32H7xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32H7xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic remap of boot address selected */ /* #define USER_VECT_TAB_ADDRESS */ #if defined(USER_VECT_TAB_ADDRESS) #if defined(CORE_CM4) /*!< Uncomment the following line if you need to relocate your vector Table in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table in D1 AXI SRAM else user remap will be done in FLASH BANK1. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7 #endif /* CORE_CM4 */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** * @} */ /** @addtogroup STM32H7xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32H7xx_System_Private_Variables * @{ */ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes * @{ */ /** * @} */ /** @addtogroup STM32H7xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the FPU setting and vector table location * configuration. * @param None * @retval None */ void SystemInit (void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ #endif /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is detectable by the CPU after a WFI/WFE instruction.*/ SCB->SCR |= SCB_SCR_SEVONPEND_Msk; #if defined(CORE_CM7) /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); } /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; /* Disable all interrupts */ RCC->CIER = 0x00000000; /* Enable CortexM7 HSEM EXTI line (line 78)*/ EXTI_D2->EMR3 |= 0x4000UL; if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } #endif /* CORE_CM7*/ #if defined(CORE_CM4) /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) { /* Enable the FMC interface clock */ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; /* Disable the FMC interface clock */ CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #else #error Please #define CORE_CM4 or CORE_CM7 #endif /* CORE_CM4 */ } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. * * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value * 4 MHz) but the real value may vary depending on the variations * in voltage and temperature. * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value * 64 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; uint32_t common_system_clock; float_t fracn1, pllvco; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ common_system_clock = CSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ common_system_clock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); if (pllm != 0U) { switch (pllsource) { case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; default: hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } else { common_system_clock = 0U; } break; default: common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; } /* Compute SystemClock frequency --------------------------------------------------*/ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; /* common_system_clock frequency : CM7 CPU frequency */ common_system_clock >>= tmp; /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #if defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; #endif /* CORE_CM4 */ } /** * @brief Exit Run* mode and Configure the system Power Supply * * @note This function exits the Run* mode and configures the system power supply * according to the definition to be used at compilation preprocessing level. * The application shall set one of the following configuration option: * - PWR_LDO_SUPPLY * - PWR_DIRECT_SMPS_SUPPLY * - PWR_EXTERNAL_SOURCE_SUPPLY * - PWR_SMPS_1V8_SUPPLIES_LDO * - PWR_SMPS_2V5_SUPPLIES_LDO * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO * - PWR_SMPS_1V8_SUPPLIES_EXT * - PWR_SMPS_2V5_SUPPLIES_EXT * * @note The function modifies the PWR->CR3 register to enable or disable specific * power supply modes and waits until the voltage level flag is set, indicating * that the power supply configuration is stable. * * @param None * @retval None */ void ExitRun0Mode(void) { #if defined(USE_PWR_LDO_SUPPLY) #if defined(SMPS) /* Exit Run* mode by disabling SMPS and enabling LDO */ PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; #else /* Enable LDO mode */ PWR->CR3 |= PWR_CR3_LDOEN; #endif /* SMPS */ /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) #if defined(SMPS) /* Exit Run* mode */ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; #else PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; #endif /* SMPS */ /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 &= ~(PWR_CR3_LDOEN); /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) /* Exit Run* mode */ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #else /* No system power supply configuration is selected at exit Run* mode */ #endif /* USE_PWR_LDO_SUPPLY */ } /** * @} */ /** * @} */ /** * @} */ - 2nd suggestion: IF 1st suggestion didn't work try to remove these 3 lines from startup_stm32h757xx_cm7.s and startup_stm32h757xx_cm4.s files (under Application/MDK-ARM)
- 3rd suggestion: If 1st and 2nd suggestion didn't work try to use an older version of TouchGFX Designer (it has to be before 4.25.0)
Hi Osman. Thank you very much for your help. Currently the compiler compiles the project without any problems.
But there is one more problem. The RIVERDI display uses external FLASH memory. I have a problem with the programming settings for this external memory. Keil only offers external flash memories from DISKO or EVAL boards.
How to create a programming file for the external flash of the RIVERDI board?
Hi.
I have tried all the presets for the 64MB external FLASH. The programming attempt always fails.
