I am trying to use the STM32H723 as a video output (tying the LTDC pins to an ADV7115 to convert them to HDMI). The idea is to read the bus traffic of an old 8-bit computer and generate the display from that traffic (as part of other duties).
My concern is that the visible-area display period on the source computer might not match the display period on this new display, so I'd like to sync them up. I don't want to triple-buffer because that would be an unacceptable delay between the 'native' and this new video output.
There's a note in the reference manual:
When the LTDC is enabled, the timings generated start with X/Y = 0/0 position as the first horizontal synchronization pixel in the vertical synchronization area and following the back porch, active data display area and the front porch.
When the LTDC is disabled, the timing generator block is reset to X = total width - 1,
Y = total height - 1 and held the last pixel before the vertical synchronization phase and the FIFO are flushed. Therefore only blanking data is output continuously
... which looks promising. Would it be possible to:
- Configure the LTDC but leave it disabled
- Once I've gathered a couple of line's worth of data from the bus, enable the LTDC and point it to the frame buffer that I'm 2 lines ahead with
- Set the LTDC line-interrupt to be the last line of the LTDC display, and disable the LTDC once it fires
... which would (ideally) output blanking data until the host computer is ready, and avoid any pre-fetch issues because the host is a couple of scanlines ahead. I'm assuming that 'enabled' here refers to bit 0 of LTDC_GCR.
That seems like it would remove any tearing possibilities (and would be as in-sync as possible), but it depends on what the startup cost is of enabling the LTDC, and I'm assuming that 320 bytes is sufficient to defeat the 16 double-word prefetch (I don't know if there's any internal cache)
Likely to work ? Or is there a better way ? 🙂
