Why mcu not reset on ESD test ?

[Mahendra Rana]

Posted on May 16, 2018 at 08:54

1. When I run system clock through HSE(8MHz/24MHz/25MHz) and PLLCLK (multiplier PLLN and divider PLLM & PLLR) than mcu not reset by ESD.

2. But when I run system clock directly through HSE(8MHz/24MHz/25MHz) than mcu get reset by ESD.

Can any one comment for my issue..

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[Mahendra Rana]

Posted on May 19, 2018 at 06:04

Please ignore comments of code.

[Tesla DeLorean]

Posted on May 19, 2018 at 06:54

You could put a reason code in an unused area of RAM, but the processor should have a reason code as to whether a reset was induced by the watchdog timer, or not.

I don't see a mention anywhere in the posting history here which STM32 specifically you're using.

[Daniel O'Neill]

Posted on May 20, 2018 at 23:54

I would do as

Turvey.Clive.002

‌ suggested. Identify an unused portion of RAM and write a different number to it before calling NVIC_SystemReset() in each of the cases in the code.

Alternatively you could replace the call to

NVIC_SystemReset() with a while() loop doing nothing. Then after an ESD zap connect with debugger and see where the PC counter is. Just be aware of the optimizer combining bits of code.

[Tesla DeLorean]

Posted on May 21, 2018 at 00:38

Hot plugging the debugger is probably less desirable, if the system can output a reason code for the reset autonomously trouble-shooting and understanding multiple systems will be easier.

It would be particularly helpful to understand if the reported reset condition was a result of the watchdog firing, because this would suggest the system actually seized up as a result of the ESD hit.

[Ran Kai]

Posted on May 24, 2018 at 12:58

One thing you could try if you have the MCO (master clock output) pin available on your board you can see what's happening on your oscilloscope during the ESD event when using PLL and compare it with without PLL.