When does memory contention occur?

[mandrake]

Posted on March 29, 2017 at 16:35

I am sure there is a simple answer to this question. DMA is accessing memory. When would there be contention for memory if the processor tries to access memory? Is it when the addresses are the same or is it when blocks of addresses overlap (i.e. same upper bits of address), and what block size? I am running STM32F407. 

#dma #memory-contention

[Tesla DeLorean]

Posted on March 29, 2017 at 17:40

When the decoded memory regions clash or the bus utilization conflicts. There should be a bus matrix diagram in the Reference Manual.

Consider you are memcpy()ing data into external memory for a video frame buffer, you also have a looping DMA task moving that data to an LCD on a different area of externally mapped memory (LCD registers), you are going to step on your own feet occasionally/frequently. Contention forces one operation to occur at a time. How frequently depend on the speed/bandwidth of the activities involved.

[mandrake]

Posted on March 29, 2017 at 17:57

Thanks, Clive.

I have an ADC sampling at 42Msps continuously. I am purposefully using a wrap-around dual-buffer DMA, 8k + 8k half-word size.

I am monitoring current target and waiting for the DMA to move from one buffer to the other before having the CPU access the off-buffer, single memory access at a time.

The purpose of all of this is to avoid memory contention. However, for my knowledge, I would like to know at what point a memory contention can occur. In other words, what is the size of memory regions that would be mutually exclusive.

[Tesla DeLorean]

Posted on March 29, 2017 at 20:13

A range of addresses within the same memory using the same 'chip select'.

ie SRAM1 being 112KB in size, SRAM 16 KB, per the RM0090 Reference Manual

For external memories in the 0x60000000..0x6FFFFFFF region you have 4 chip selects describing 0x04000000 (64MB) blocks

See also 'Figure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices'

What can you possibly do with data at a 42Msps rate? Drinking from a firehose

[mandrake]

Posted on March 29, 2017 at 21:05

'chip select' - Shucks, I thought you were on to something there! But no joy!

I went and checked my memory assignments. I am already splitting the two 8k buffers across SRAM1 and SRAM2.

1st buffer in SRAM1 @ 0x2001 8000

2nd buffer in SRAM2 @ 02001 C000

'What can you possibly do with data at a 42Msps rate? Drinking from a firehose'

I am doing digital signal processing, capturing nuclear signals with fast rise-times.

[Tesla DeLorean]

Posted on March 29, 2017 at 22:32

But you simple don't have the bandwidth to sustain that kind of rate, on a long term continuous basis, or do any reading/writing/computation.

[mandrake]

Posted on March 29, 2017 at 23:07

I don't know what you mean by that. I don't think you understand.

I have this already working.

It is a DSP system that analyses nuclear radiation pulses, samples the analog signal at 42Msps, collects, analyzes, and displays the energy spectrum AND displays the analog waveform on a SVGA display all in REAL TIME using a single STM32F407.

Bandwidth simply is not an issue here.

I am simply tweaking the system where I am trying to avoid memory contention.

I have managed to solve most of this by moving all variables to core-coupled memory, and you assisted me in doing this.

[Tesla DeLorean]

Posted on March 29, 2017 at 23:52

>>I don't know what you mean by that. I don't think you understand. I have this already working.

Perhaps, but I think you are periodically sampling/processing at 42Msps, not continuously, in the leave no sample behind sense, and do a lot of work with 4 cycles per sample

[mandrake]

Posted on March 30, 2017 at 00:17

Aha! That is where you don't have all the information.

I have data at 42Msps, continuous, non-stop.

But I don't have to analyze all data points. I can pick and choose which data to examine.

With 8k samples at 42Msps, I have 200us worth of data. I can process this data in under 100us.

Don't worry. This part is working fine. I am able to monitor the progress of the analysis algorithm and witness how long the process is taking. I works 90% of the time. For the 10% I can see when the processor takes an access hit and the processor slows down. That's why I need to know when and where memory contention occurs.

[mandrake]

Posted on March 30, 2017 at 00:48

Ok, I've figured it out. The information you supplied was instrumental in solving this riddle. Thanks for your help once again.