Hi,
I have one board where, depending on PLL configuration, it yields a lot of seed errors on RNG
This is the faulty configuration
RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL1.PLLFractional = 0;
RCC_OscInitStruct.PLL1.PLLM = 4;
RCC_OscInitStruct.PLL1.PLLN = 50; /* VCO = HSI/M * N = 16 / 4 * 50 = 200 MHz */
RCC_OscInitStruct.PLL1.PLLR = 2; /* PLLSYS = 200 MHz / 2 = 100 MHz */
RCC_OscInitStruct.PLL1.PLLP = 2;
RCC_OscInitStruct.PLL1.PLLQ = 8; /* 25 MHz */
If I change PLLQ to 7 or 9, issue is gone.fff
From RM: RNG dedicated clock, asynchronous to rng_hclk
- Is it the ratio 100 MHz / 25 MHz just a bad ratio?
- Why is it an issue only in one board?
