Want to generate pulse train of progressively increasing pulse duration in response to trigger train.

[fshah48]

Posted on April 06, 2017 at 11:50

Want to generate pulse train of progressively increasing pulse duration in response to a trigger train. OPM seems o be solution. Can I change CCR1 and ARR register values in interrupt routine to change 'delay' and 'pulse duration'?

[Tesla DeLorean]

Posted on April 06, 2017 at 15:06

>>Can I change CCR1 and ARR register values in interrupt routine to change 'delay' and 'pulse duration'?

Yes, typically in the Update handler, with the shadowing you are one period behind. Set the pulse width to zero to turn off.

The advanced timers also have a repetition count, so multiple pulses can be sent between Update interrupts.

[S.Ma]

Posted on April 06, 2017 at 21:41

How about a one shot timer mode triggered by channel input 1 or 2, and output pulse value is set by a serial table pushed by dma on the output compare register to ouput gpios? Would work even with khz periodic signals...

[fshah48]

Posted on April 06, 2017 at 20:56

Hi Clive

Le me make the problem a bit more clear. I have a trigger waveform approx

20ms period with 50% duty cycle. I must generate a constant width pulse on

each trigger edge but progressively decreasing delay.

I don't understand 'shadowing'?

I was hoping to set CCR1 and ARR to starting values, and decrease CCR1 and

ARR registers in the handler. Hoping to get output pulses of constant

width(100us) and varying delay (starting from 8000us down to 20us.

fshah48

On Thu, Apr 6, 2017 at 6:07 PM, Clive One <st-microelectronics@jiveon.com>

[Tesla DeLorean]

Posted on April 06, 2017 at 22:04

Shadowing just means it starts using the new data at zero phase angle (update), rather than some random time within the current cycle, which could glitch the pulse width.

If the pulse width remains constant, then you don't need to reprogram CCR1. Have DMA load ARR automatically at Update, and have a memory table describing smaller and smaller values for the Period. Or use the IRQ.

[fshah48]

Posted on April 06, 2017 at 22:19

Hello Clive

Thanks for explanation of shadowing.

I believe both CCR1 and ARR both need to change because delay=CCR1 and

pulse width=ARR - CCR1 according to manual. I am using discovery board, it

does not allow burst DMA, thus I must make change in IRQ handler. Can I do

that without causing glitch. My hunch is that registers should be updated

while timer is waiting for external trigger, This could be achieved by an

IRQ handler that is fired by down going edge of the pulse(goes inactive)

which will use another channel. Please comment on this solution and

provide a better solution if any. Thanks in advance.

fshah48

On Fri, Apr 7, 2017 at 1:05 AM, Clive One <st-microelectronics@jiveon.com>