USART RX with DMA, FIFO and NDTR

[Greg K.]

Posted on May 24, 2017 at 03:21

Hello,

I would like to use an USART with DMA (peripheral to memory) with FIFO enabled in a circular mode on the STM32F205.

My stream of data is pretty random and I would like to process the memory buffered data on the fly.

The problem is that the NDTR value is taking into account also the data in the FIFO, so that I can not know how much data is in the memory.

Is there any way to know the exact amount of data in memory and the exact state of the FIFO on the fly in the program?

Kind regards,

Greg

[waclawek.jan · Accepted solution]

Posted on May 24, 2017 at 16:19

The data in memory can be found by getting value from NDTR and truncating it modulo FIFO size.

That would be,

https://community.st.com/0D50X00009XkhAxSAJ

. That's why in my programs I assume NDTR is decremented one less than it is acutally (and only after that correction I perform the truncation if FIFO is involved).

JW

[Greg K.]

Posted on May 24, 2017 at 17:08

Thank you for the reply.

I already read the linked thread, but I don't see a suitable solution.

If I assume NDTR is decremented one less that it is, then if my data stream stops I will never process the last received data. If I wait and assume that I got everything if NDTR is not changing, then I am wasting time.

Is there any variable that is showing the state of the FIFO?

[waclawek.jan]

Posted on May 25, 2017 at 01:52

If I assume NDTR is decremented one less that it is, then if my data stream stops I will never process the last received data.

Yes. I use continuous data, I understand that's a difference.

Nonetheless, with discontinuous data, you'll still have data remaining in the FIFO most of the time; and I know of no other way how to flush it except stop the DMA (which can't be 'continued' only 'restarted', and often that's a nuisance to be avoided). So, at the end of the day, you don't really want to use the FIFO.

If I wait and assume that I got everything if NDTR is not changing, then I am wasting time.

Yes.

To avoid the problem from that thread, you don't need to check if NDTR is not changing, simply wait long enough for DMA to succeed to actually move the data to RAM. Often there's enough reasonable work to do between NDTR read and data read so that it may be not just wasted time; but even then, the main issue is, that it's not trivial to determine how long one has to wait. Far from it, especially in heavily loaded systems with multiple DMA streams running.

Is there any variable that is showing the state of the FIFO?

Yes. NDTR ( transferred mod FIFO size).

JW

[Greg K.]

Posted on May 25, 2017 at 23:54

Thank you again for the response.

I thought that the DMA FIFO flushed itself as soon as the DMA controller was idle, but I was wrong.

Now I see that it doesn't make sense to use the DMA FIFO if you don't have a continuous data stream.