2011-09-13 12:10 AM
Posted on September 13, 2011 at 09:10
Sometimes my code gets lost in usart1 interrupt flood.
Registers:
CR1: 0x202c (UE, RXNEIE, TE, RE)
CR2 = 0, CR3 = 0
SR: 0x1d8 (LBD, TXE, TC, IDLE, ORE)
I'm not quite getting it how ORE can be set and RXNE not. The only thing that comes to mind is that ORE gets set between reading SR (RXNE=1, ORE=0), and reading DR.
But how is ORE supposed to be cleared if DR is empty then? Read SR then read (the empty!) DR?
# worst-forum-software-ever
2011-09-13 04:28 AM
Indeed the USART will not receive data when an error condition is pending.
You need to check the SR for RXNE and all the receive error bits, you must read DR to clear the error state, when RXNE is 0 you should discard the data. The manual does state that a read of DR is required, as I recall. I tend to observe over-run conditions when writing/erasing flash while executing from flash, as the processor blocks for periods exceeding the USART byte time. Parity and Framing Errors will also do this.2011-09-13 07:31 AM
Thanks, I'm reading and discarding DR now (I still think this is wtf).
Oh, btw. it appears USART_GetITStatus(foo, USART_IT_ORE) always returns 0... itmask calculates to 0, and I have no idea what it was supposed to calculate to, since CR3 doesn't seem to be the right register anyways.2011-09-13 08:04 AM
I guess they really don't want you to miss/ignore the error. The example code is very bad in this regard as it assumes error free operation, which is always an awful plan for robust code.
Can't speak to the IT status bits, I'm using RX/TX interrupts, and periodically checking if the TX interrupt needs to be re-enabled. #define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE) void Uart_EmptyRx(UART *Uart) { USART_TypeDef *Port = Uart->Port; WORD status; status = Port->SR; while(status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) { BYTE ch; ch = Port->DR; // Read Data, or Clear Error(s) if (status & USART_FLAG_ERRORS) Uart->Errors++; else Fifo_Insert(Uart->Rx, sizeof(ch), &ch); status = Port->SR; }...
}2014-09-30 12:45 AM
Posted on September 30, 2014 at 09:45
lee.paul.003 above succeeded in creating a '
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' [EDIT] probably this:
https://community.st.com/0D50X00009XkgczSAB
[/EDIT], which may be of interest to the OP, and which (at least for me) does not appear in this post list nor in the main list of threads (I follow the forum through RSS feed which appears to display all individual posts).
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