Posted on December 16, 2011 at 05:26(Mod, this is more of a blog type post. Yet my experience may be useful to some here. Is there a better place to post?)
I am comparing my STM32F10xxE eval board with the F4 Discovery board.
Bottom line: F4 is much faster & changing I/O was a pain.
Most of the I/O is different between F1 and F4 parts. How ST could claim compatibility with older products with a straight face is beyond me. Did product design engineering’s input on compatibility fall on deaf sales force ears?
Fortunately my application is an RTOS. Thus the only required changes were in the area of setting wait states and the main PLL. I did it all in assembly. I optimized for size in initialization.
But an RTOS is hard to test without some sort of application. I used the DTMF decode part of a telephony application that, alas, is not likely to be funded. That application code reads 4 ADC voice channels (8KHz sample rate) looking for DTMF tones. My ADC uses DMA in circular buffer mode. Tones are decoded using the Goertzel algorithm on 100 points.
I used “#if __CORE__ = __ARM7EM__� conditional assembly so that the same code would work on both processors. To keep things simpler I set the F4 SYSCLK to 72MHz.
Interrupt vectors: some are the same, some have moved and there are interspersed new items. The same is true about the various peripheral enables.
DMA: From RM0900 it appears that PFCTRL in DMA_CR, “1: The peripheral is the flow controller�, should be set. Apparently my guess as to what “flow controller� means was wrong. PFCTLR=0 had to be used. Until I changed it CIRC refused to set and DMA_NDTR changed to 0xFFFF. Not nice.
ADC: In ADC_CR2 the DDS bit had to be set. Go ahead and read RM0090 for this bit. It looked all the world like this bit should be clear.
Debug registers:
F1: set location 0xE0042004 to 0x001E3C00 to stop all timers when the CPU core is stopped. Use the same code in an F4 and things freeze far enough into the code that the F1 code is not suspected.
F4: set location 0xE0042008 to 0x1DFF to stop t2-t7,t12-t14 & 3 more timers.
(Stopping at least the timer that triggers ADC is important if you use a debugger.)
Wait states:
After measuring DTMF decode times using systick (0xE000E018) it was time to change flash wait states from 5 to 2. That change failed. So measurements with 5 wait states are given.
F1 @72Mhz 0.60 milliseconds (2 wait states used here)
F4 @72MHz 0.39 milliseconds (without H/W floating point)
F4 @72MHz 0.053 milliseconds (with H/W floating point & hand coded FPU Goertzel algorithm)
It looks like the ART Acceleratorâ„¢ was really helping.
Bottom line: F4 is much faster & changing from an F1 was a pain.
