Ultra low powered STM32

[gdp123a]

Posted on January 07, 2008 at 13:55

Ultra low powered STM32

[gdp123a]

Posted on May 17, 2011 at 12:20

First I want to say how much I like this chip, I've been waiting for a chip like this for years.

It sounds like newer versions of this chip will be released this year (eg. more RAM, more FLASH, more pins etc.) I want to put in a wish for a new version at the lower end of the scale. When the chip is in Sleep mode, running at 1MHz (or slower) using the HSI, the chip uses 440 micro amps. I'm curious, where is this current being used? It would be great to have a special version of the STM32 dedicated to ultra low power applications. I'm not sure what would have to be changed to reduce the power consumption further - perhaps setting the maximum clock frequency to 8MHz, or reducing the accuracy of the HSI, or limiting the amount of RAM and FLASH. I would be happy to live with these and possibly other limitations to reduce power consumption. If it was only available in the 36 pin package that would be fine too. Many of my applications run off lithium coin cells, which can't supply much current without having the voltage drop noticeably. For example, assuming a peak maximum supply current of 1 milliamp, I could run a TI MSP430F149 at around 4MHz or the STM32 at 1MHz. From my rough calculations and testing I would be able to do more taps of an FIR filter using the MSP430F149 (although once I become more familiar with STM32 assembler code I might be able reverse this situation). An ultra-low powered STM32 would allow people to use one architecture for all types of applications. thanks. Greg. PS. An assembler reference manual just for the Cortex-M3 would be nice too.

[asterix]

Posted on May 17, 2011 at 12:20

Hi Greg,

Quote:

When the chip is in Sleep mode, running at 1MHz (or slower) using the HSI, the chip uses 440 micro amps. I'm curious, where is this current being used? Many of my applications run off lithium coin cells, which can't supply much current without having the voltage drop noticeably. . Looking on the Sleep Mode, I believe that the 440µA was measured with a VDD at 3.3 Volts (Typical) and should be less if using 3Volts, In this mode only the CPU is OFF and in case we disable all peripherals, I presume that this 440µA is the static Comsumption of the Analog blocks like the Voltage regulator, Buses and memories (Flash and SRAM) which are powered in this Mode waiting any Interrupt/Event to Fire the CPU. For battery Coin application, the STOP and Standby are more powerful to have better battery life. this is detailed in this App Note from ST Web site : AN2629 STM32F101xx and STM32F103xx low-power modes

Quote:

For example, assuming a peak maximum supply current of 1 milliamp, I could run a TI MSP430F149 at around 4MHz or the STM32 at 1MHz. From my rough calculations and testing I would be able to do more taps of an FIR filter using the MSP430F149 (although once I become more familiar with STM32 assembler code I might be able reverse this situation). . I have customized, in my STM32 evaluation, the attached FIR filter in assembly (working with Keil µVision) found on web, for Cortex-M3 and I can have up to 16 TAPs in a raw for 16-bits data. Do you have some comparison results for this FIR between MSP430 and STM32? For Cortex-M3 assembly instructions you can refer to www.arm.com then search for Thumb2 and cortex-M3 manuals. Magigimix 8-) [ This message was edited by: asterix.magigimix on 06-01-2008 17:07 ]

[gdp123a]

Posted on May 17, 2011 at 12:20

Hi Magigimix

yes I agree, the Stop and Standby modes are a great way of saving power if the processor has spare time on its hands. However, sometimes there is no spare time and the processor has to run continually, especially if you're trying to do a lot filtering with very little current. I mentioned the 440uA power consumption during sleep mode (with all peripherals disabled, fHCLK= 1MHz) because it gave a good indication of the background power drain when not much is happening. It took me 26 cycles to do an FIR tap with circular buffering on the TI MSP430F149. AFter refining my code, it takes me now 6 cycles per tap on the STM (this is using a jump table to avoid loop overheads). This does not include the overhead of setting up the jumps, but it does handle circular buffering. After a closer look at the data sheet for the MSP430F149 I realise that the current at 3V is a fair bit higher than I remembered - and that the STM32 current figures are specified at 3.3V So I might not be able to make a proper comparison until I can run the chip on my own PCB (with no regulator - just a battery). Greg.

[obtronix]

Posted on May 17, 2011 at 12:20

greg,

a few thoughts to ponder 1) the voltage at which the power consumption is measured (see someone else mentioned this)needs to be taken into account 2)The MSP430F149 HW multiple takes 10 cycles are so to load up for each 16 bit multiply (even though the multipy itself is only 1 cycle), the STM has a single cycle 32 bit multiply 3) The MSP and AVR can run down to 32Khz and use very little power (40uA), the STM32 tends to have a min idle power at 500uA. If you have 1mA of current available this means the most efficient way to use the STM is in standby mode (with RTC running, a few uA), use the RTC to wake up the processor, then jump to a high Speed, say 2MHz (1.6mA) for a short period of time, then jump back down to standby so the total average current is 1mA. I think a coin cell has no problems with this. This processor is MUCH more efficient (mips/watt) at 2Mhz vs 125Khz. Of course all the above depends on what peripherals you need running and if you can lose SRAM during standby (STM only has backup RAM during standby). If you can't lose RAM then MSP are king.